Issued Patents All Time
Showing 426–450 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10559692 | Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor | Xin Miao, Jingyun Zhang, Choonghyun Lee | 2020-02-11 |
| 10559672 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-02-11 |
| 10559671 | Vertical transport field-effect transistor including air-gap top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-02-11 |
| 10553708 | Twin gate tunnel field-effect transistor (FET) | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-02-04 |
| 10553696 | Full air-gap spacers for gate-all-around nanosheet field effect transistors | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2020-02-04 |
| 10553679 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-02-04 |
| 10553678 | Vertically stacked dual channel nanosheet devices | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando | 2020-02-04 |
| 10553586 | Stacked complementary junction FETs for analog electronic circuits | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-02-04 |
| 10546928 | Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques | Pouya Hashemi, Karthik Balakrishnan, Mahmoud Khojasteh | 2020-01-28 |
| 10546925 | Vertically stacked nFET and pFET with dual work function | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-01-28 |
| 10546918 | Multilayer buried metal-insultor-metal capacitor structures | Joshua M. Rubin, Oscar van der Straten, Praneet Adusumilli | 2020-01-28 |
| 10546915 | Buried MIM capacitor structure with landing pads | Praneet Adusumilli, Oscar van der Straten, Joshua M. Rubin | 2020-01-28 |
| 10546857 | Vertical transistor transmission gate with adjacent NFET and PFET | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-01-28 |
| 10546815 | Low resistance interconnect structure with partial seed enhancement liner | Oscar van der Straten, Joseph F. Maniscalco, Koichi Motoyama | 2020-01-28 |
| 10541335 | Stress induction in 3D device channel using elastic relaxation of high stress material | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2020-01-21 |
| 10541242 | Vertical transistor with eDRAM | — | 2020-01-21 |
| 10541207 | Biconvex low resistance metal wire | Praneet Adusumilli, Oscar van der Straten | 2020-01-21 |
| 10541203 | Nickel-silicon fuse for FinFET structures | Kangguo Cheng, Keith E. Fogel, Pouya Hashemi | 2020-01-21 |
| 10541202 | Programmable buried antifuse | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2020-01-21 |
| 10529716 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Choonghyun Lee, Jingyun Zhang, Takashi Ando, Pouya Hashemi | 2020-01-07 |
| 10529828 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2020-01-07 |
| 10522678 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-12-31 |
| 10522419 | Stacked field-effect transistors (FETs) with shared and non-shared gates | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2019-12-31 |
| 10522421 | Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation | — | 2019-12-31 |
| 10510829 | Secondary use of aspect ratio trapping trenches as resistor structures | Chih-Chao Yang, Praneet Adusumilli, Oscar van der Straten | 2019-12-17 |