Issued Patents All Time
Showing 451–475 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10504900 | Enhanced field Resistive RAM integrated with nanosheet technology | Pouya Hashemi, Takashi Ando | 2019-12-10 |
| 10483361 | Wrap-around-contact structure for top source/drain in vertical FETs | Choonghyun Lee, Christopher J. Waskiewicz, Hemanth Jagannathan | 2019-11-19 |
| 10483368 | Single crystalline extrinsic bases for bipolar junction structures | Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau | 2019-11-19 |
| 10468311 | Nanosheet substrate isolated source/drain epitaxy by nitrogen implantation | — | 2019-11-05 |
| 10468503 | Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices | Karthik Balakrishnan, Jeng-Bang Yau, Tak H. Ning | 2019-11-05 |
| 10468532 | Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor | Xin Miao, Jingyun Zhang, Choonghyun Lee | 2019-11-05 |
| 10468585 | Dual function magnetic tunnel junction pillar encapsulation | Son V. Nguyen, Donald F. Canaperi | 2019-11-05 |
| 10461148 | Multilayer buried metal-insultor-metal capacitor structures | Joshua M. Rubin, Oscar van der Straten, Praneet Adusumilli | 2019-10-29 |
| 10453959 | Fin replacement in a field-effect transistor | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Dominic J. Schepis | 2019-10-22 |
| 10453792 | High density antifuse co-integrated with vertical FET | Pouya Hashemi, Miaomiao Wang, Takashi Ando | 2019-10-22 |
| 10446746 | ReRAM structure formed by a single process | Oscar van der Straten, Adra Carr, Praneet Adusumilli | 2019-10-15 |
| 10438956 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi | 2019-10-08 |
| 10439063 | Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices | Shogo Mochizuki, Jingyun Zhang, Xin Miao | 2019-10-08 |
| 10438858 | Low-cost SOI FinFET technology | Stephen W. Bedell, Joel P. de Souza, Devendra K. Sadana, Dominic J. Schepis | 2019-10-08 |
| 10439049 | Nanosheet device with close source drain proximity | Veeraraghavan S. Basker, Shogo Mochizuki | 2019-10-08 |
| 10431542 | Low resistance seed enhancement spacers for voidless interconnect structures | Praneet Adusumilli, Joseph F. Maniscalco, Oscar van der Straten | 2019-10-01 |
| 10424585 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-09-24 |
| 10424650 | Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2019-09-24 |
| 10410966 | BEOL embedded high density vertical resistor structure | Oscar van der Straten, Praneet Adusumilli | 2019-09-10 |
| 10411109 | Bipolar junction transistor (BJT) for liquid flow biosensing applications without a reference electrode and large sensing area | Tak H. Ning, Sufi Zafar, Oscar van der Straten | 2019-09-10 |
| 10396075 | Very narrow aspect ratio trapping trench structure with smooth trench sidewalls | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-08-27 |
| 10396165 | Thin low defect relaxed silicon germanium layers on bulk silicon substrates | Praneet Adusumilli, Keith E. Fogel, Oscar van der Straten | 2019-08-27 |
| 10396202 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2019-08-27 |
| 10396214 | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz | 2019-08-27 |
| 10396152 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2019-08-27 |