Issued Patents All Time
Showing 326–350 of 1,279 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10825916 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-11-03 |
| 10825921 | Lateral bipolar junction transistor with controlled junction | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2020-11-03 |
| 10825736 | Nanosheet with selective dipole diffusion into high-k | Jingyun Zhang, Takashi Ando, Choonghyun Lee | 2020-11-03 |
| 10818753 | VTFET having a V-shaped groove at the top junction region | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2020-10-27 |
| 10811410 | Simultaneously fabricating a high voltage transistor and a FinFET | Kangguo Cheng, Ali Khakifirooz, Charan V. V. S. Surisetty | 2020-10-20 |
| 10804278 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi | 2020-10-13 |
| 10804382 | Integrated ferroelectric capacitor/field effect transistor structure | Takashi Ando, Pouya Hashemi | 2020-10-13 |
| 10790357 | VFET with channel profile control using selective GE oxidation and drive-out | Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee | 2020-09-29 |
| 10784258 | Selective contact etch for unmerged epitaxial source/drain regions | Sanjay C. Mehta | 2020-09-22 |
| 10784371 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki | 2020-09-22 |
| 10784194 | BEOL embedded high density vertical resistor structure | Oscar van der Straten, Praneet Adusumilli | 2020-09-22 |
| 10777555 | Low voltage (power) junction FET with all-around junction gate | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-09-15 |
| 10777679 | Removal of work function metal wing to improve device yield in vertical FETs | Choonghyun Lee, Soon-Cheon Seo, Injo Ok | 2020-09-15 |
| 10777464 | Low thermal budget top source and drain region formation for vertical transistors | Shogo Mochizuki, Oleg Gluschenkov | 2020-09-15 |
| 10770461 | Enhanced field resistive RAM integrated with nanosheet technology | Pouya Hashemi, Takashi Ando | 2020-09-08 |
| 10763343 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Shogo Mochizuki | 2020-09-01 |
| 10763177 | I/O device for gate-all-around transistors | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-09-01 |
| 10755985 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Joshua M. Rubin, Junli Wang | 2020-08-25 |
| 10756216 | Nanosheet mosfet with isolated source/drain epitaxy and close junction proximity | Xin Miao, Choonghyun Lee, Jingyun Zhang | 2020-08-25 |
| 10756097 | Stacked vertical transistor-based mask-programmable ROM | Karthik Balakrishnan, Tak H. Ning, Bahman Hekmatshoartabari | 2020-08-25 |
| 10756163 | Conformal capacitor structure formed by a single process | Praneet Adusumilli, Oscar van der Straten | 2020-08-25 |
| 10756176 | Stacked nanosheet technology with uniform Vth control | Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee | 2020-08-25 |
| 10748819 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Choonghyun Lee, Sanghoon Shin, Jingyun Zhang, Pouya Hashemi | 2020-08-18 |
| 10748990 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh | 2020-08-18 |
| 10748994 | Vertically stacked nFET and pFET with dual work function | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-08-18 |