Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10381260 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 10381261 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 10283402 | Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress | Gang Wang, Jeffrey L. Libbert, Shawn George Thomas | 2019-05-07 |
| 10269617 | High resistivity silicon-on-insulator substrate comprising an isolation region | Jeffrey L. Libbert | 2019-04-23 |
| 10083855 | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition | Illaria Katia Marianna Pellicano | 2018-09-25 |
| 10079170 | High resistivity SOI wafers and a method of manufacturing thereof | Srikanth Kommu, Gang Wang, Shawn George Thomas | 2018-09-18 |
| 9831115 | Process flow for manufacturing semiconductor on insulator structures in parallel | Andrew M. Jones, Srikanth Kommu, Jeffrey L. Libbert | 2017-11-28 |
| 9768056 | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition | Illaria Katia Marianna Pellicano | 2017-09-19 |
| 9640666 | Integrated circuit employing variable thickness film | — | 2017-05-02 |
| 8987102 | Methods of forming a metal silicide region in an integrated circuit | Michael G. Ward | 2015-03-24 |
| 8802522 | Methods to adjust threshold voltage in semiconductor devices | Michael G. Ward, Sunny Chiang, Yen B. Ta, Andrew Darlak, Peter I. Porshnev +1 more | 2014-08-12 |
| 8143138 | Method for fabricating interconnect structures for semiconductor devices | Ryan Patz, Jeremiah T. Pender, Michael D. Armacost | 2012-03-27 |
| 8039878 | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | Thorsten Kammler, Andy Wei | 2011-10-18 |
| 7902008 | Methods for fabricating a stressed MOS device | Mario M. Pelella | 2011-03-08 |
| 7893496 | Stress enhanced transistor | Rohit Pal | 2011-02-22 |
| 7767540 | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | Thorsten Kammler, Andy Wei | 2010-08-03 |
| 7754554 | Methods for fabricating low contact resistance CMOS circuits | Patrick Press, Paul R. Besser | 2010-07-13 |
| 7704840 | Stress enhanced transistor and methods for its fabrication | Rohit Pal | 2010-04-27 |
| 7696534 | Stressed MOS device | Linda Black, Frank Wirbeleit | 2010-04-13 |
| 7635648 | Methods for fabricating dual material gate in a semiconductor device | Victor Ku, Joe Piccirillo | 2009-12-22 |
| 7605045 | Field effect transistors and methods for fabricating the same | Patrick Press, Rolf Stephan | 2009-10-20 |
| 7534689 | Stress enhanced MOS transistor and methods for its fabrication | Rohit Pal, David E. Brown | 2009-05-19 |
| 7494918 | Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof | Byeong Y. Kim, Xiaomeng Chen, Judson R. Holt, Christopher D. Sheraw, Linda Black | 2009-02-24 |
| 7462524 | Methods for fabricating a stressed MOS device | Martin Gerhardt, David E. Brown | 2008-12-09 |
| 7456058 | Stressed MOS device and methods for its fabrication | Linda Black, Huicai Zhong | 2008-11-25 |