Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11699615 | High resistivity semiconductor-on-insulator wafer and a method of manufacture | Igor Peidous, Lu Fei, Jeffrey L. Libbert, Alex Usenko, Gang Wang +2 more | 2023-07-11 |
| 11508612 | Semiconductor on insulator structure comprising a buried high resistivity layer | Igor Peidous, Srikanth Kommu, Horacio Josue Mendez | 2022-11-22 |
| 11145538 | High resistivity silicon-on-insulator structure and method of manufacture thereof | Jeffery L. Libbert, Qingmin Liu, Gang Wang | 2021-10-12 |
| 11139198 | High resistivity semiconductor-on-insulator wafer and a method of manufacturing | Igor Peidous, Lu Fei, Jeffrey L. Libbert, Alex Usenko, Gang Wang +2 more | 2021-10-05 |
| 10622247 | Semiconductor on insulator structure comprising a buried high resistivity layer | Igor Peidous, Srikanth Kommu, Horacio Josue Mendez | 2020-04-14 |
| 10483152 | High resistivity semiconductor-on-insulator wafer and a method of manufacturing | Igor Peidous, Lu Fei, Jeffrey L. Libbert, Alex Usenko, Gang Wang +2 more | 2019-11-19 |
| 10468294 | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface | Igor Peidous, Srikanth Kommu, Gang Wang, Jeffrey L. Libbert | 2019-11-05 |
| 10468295 | High resistivity silicon-on-insulator structure and method of manufacture thereof | Jeffery L. Libbert, Qingmin Liu, Gang Wang | 2019-11-05 |
| 10381260 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 10381261 | Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers | Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Samuel Christopher Pratt, Horacio Josue Mendez +2 more | 2019-08-13 |
| 9831115 | Process flow for manufacturing semiconductor on insulator structures in parallel | Igor Peidous, Srikanth Kommu, Jeffrey L. Libbert | 2017-11-28 |
| 8859393 | Methods for in-situ passivation of silicon-on-insulator wafers | Michael J. Ries, Dale A. Witte, Anca Stefanescu | 2014-10-14 |