Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11387353 | Structure providing charge controlled electronic fuse | Sudarshan Narayanan, Alvin J. Joseph, William J. Taylor, Jr., Jeffrey B. Johnson | 2022-07-12 |
| 11276770 | Gate controlled lateral bipolar junction/heterojunction transistors | Mankyu Yang, Alexander L. Martin, John J. Ellis-Monaghan | 2022-03-15 |
| 11195947 | Semiconductor device with doped region adjacent isolation structure in extension region | Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson, Srikanth B. Samavedam | 2021-12-07 |
| 11164978 | High-voltage diode finFET platform designs | Sudarshan Narayanan | 2021-11-02 |
| 11152496 | IC structure base and inner E/C material on raised insulator, and methods to form same | Alexander L. Martin, Alexander M. Derrickson | 2021-10-19 |
| 11133397 | Method for forming lateral heterojunction bipolar devices and the resulting devices | Alexander L. Martin | 2021-09-28 |
| 11127843 | Asymmetrical lateral heterojunction bipolar transistors | Judson R. Holt, Alexander M. Derrickson, Ryan Sporer, George R. Mulfinger, Alexander L. Martin | 2021-09-21 |
| 11127818 | High voltage transistor with fin source/drain regions and trench gate structure | Srikanth B. Samavedam | 2021-09-21 |
| 11094805 | Lateral heterojunction bipolar transistors with asymmetric junctions | Alexander M. Derrickson, Edmund K. Banghart, Alexander L. Martin, Ryan Sporer, Katherina Babich +1 more | 2021-08-17 |
| 11049955 | Epi semiconductor material structures in source/drain regions of a transistor device formed on an SOI substrate | Shesh Mani Pandey, Judson R. Holt | 2021-06-29 |
| 10896953 | Diode structures | Shiv Kumar Mishra | 2021-01-19 |
| 10879171 | Vertically oriented metal silicide containing e-fuse device | Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Hui Zang | 2020-12-29 |
| 10832842 | Insulating inductor conductors with air gap using energy evaporation material (EEM) | Sunil Kumar Singh | 2020-11-10 |
| 10833183 | Interlayer ballistic transport semiconductor devices | Joshua F. Dillon, Siva P. Adusumilli, Anthony K. Stamper, Laura J. Schutz | 2020-11-10 |
| 10699961 | Isolation techniques for high-voltage device structures | Edward J. Nowak | 2020-06-30 |
| 10644149 | LDMOS fin-type field-effect transistors including a dummy gate | Jerome Ciavatti | 2020-05-05 |
| 10593754 | SOI device structures with doped regions providing charge sinking | Jerome Ciavatti, Jae Gon Lee, Josef S. Watts | 2020-03-17 |
| 10546943 | Methods, apparatus, and system for reducing leakage current in semiconductor devices | Arkadiusz Malinowski | 2020-01-28 |
| 10510662 | Vertically oriented metal silicide containing e-fuse device and methods of making same | Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Hui Zang | 2019-12-17 |
| 10475921 | Laterally diffused field effect transistor and a method of manufacturing the same | — | 2019-11-12 |
| 10461029 | Hybrid material electrically programmable fuse and methods of forming | Chun Yu Wong | 2019-10-29 |
| 10453605 | Insulating inductor conductors with air gap using energy evaporation material (EEM) | Sunil Kumar Singh | 2019-10-22 |
| 10332834 | Semiconductor fuses with nanowire fuse links and fabrication methods thereof | Chun Yu Wong, Ashish Baraskar, Min-hwa Chi | 2019-06-25 |
| 10290712 | LDMOS finFET structures with shallow trench isolation inside the fin | Jerome Ciavatti, Hui Zang | 2019-05-14 |
| 10290698 | Substrate resistor with overlying gate structure | — | 2019-05-14 |