Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520396 | Method for making high voltage integrated circuit devices in a fin-type process and resulting devices | — | 2016-12-13 |
| 9508795 | Methods of fabricating nanowire structures | Chun Yu Wong, Min-hwa Chi, Ashish Baraskar | 2016-11-29 |
| 9508743 | Dual three-dimensional and RF semiconductor devices using local SOI | Srikanth B. Samavedam | 2016-11-29 |
| 9455316 | Three-dimensional electrostatic discharge semiconductor device | Andy Wei, Mahadeva Iyer Natarajan | 2016-09-27 |
| 9437713 | Devices and methods of forming higher tunability FinFET varactor | Andy Wei, Gopal Srinivasan, Amaury Gendron | 2016-09-06 |
| 9418993 | Device and method for a LDMOS design for a FinFET integrated circuit | — | 2016-08-16 |
| 9349718 | ESD snapback based clamp for finFET | Andy Wei, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Anil Kumar | 2016-05-24 |
| 9343456 | Metal gate for robust ESD protection | Amaury Gendron-Hansen, Andy Wei | 2016-05-17 |
| 9330971 | Method for fabricating integrated circuits including contacts for metal resistors | Scott Beasor | 2016-05-03 |
| 9324827 | Non-planar schottky diode and method of fabrication | Jerome Ciavatti | 2016-04-26 |
| 9312371 | Bipolar junction transistors and methods of fabrication | — | 2016-04-12 |
| 9276088 | Method for making high voltage integrated circuit devices in a fin-type process and resulting devices | — | 2016-03-01 |
| 9263385 | Semiconductor fuses and fabrication methods thereof | Anurag Mittal | 2016-02-16 |
| 9230913 | Metallization layers configured for reduced parasitic capacitance | Biswanath Senapati, Karthik Chandrasekaran | 2016-01-05 |
| 9177951 | Three-dimensional electrostatic discharge semiconductor device | Andy Wei, Mahadeva Iyer Natarajan | 2015-11-03 |
| 8946039 | Polysilicon resistor formation | Shesh Mani Pandey, Roderick Miller, Nam Sung Kim | 2015-02-03 |
| 8476684 | Field effect transistors having improved breakdown voltages and methods of forming the same | Edward John Coyne, Paul Malachy Daly, Seamus P. Whiston, Patrick Martin McGuinness, William Allan Lane | 2013-07-02 |
| 7504328 | Schottky barrier source/drain n-mosfet using ytterbium silicide | Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Li, Chunxiang Zhu +1 more | 2009-03-17 |
| 7002175 | Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration | Yong-Tian Hou, Ming Li | 2006-02-21 |