Issued Patents All Time
Showing 126–146 of 146 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8519445 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang +2 more | 2013-08-27 |
| 8466062 | TSV backside processing using copper damascene interconnect technology | Yue Kang Lu, Shaoning Yuan, Yeow Kheng Lim | 2013-06-18 |
| 8358007 | Integrated circuit system employing low-k dielectrics and method of manufacture thereof | Dong Kyun Sohn, Wuping Liu, Fan Zhang, Jing Hui Li, Bei Chao Zhang +3 more | 2013-01-22 |
| 8102054 | Reliable interconnects | Bei Chao Zhang, Chim Seng Seet, Fan Zhang, Yong Chiang EE, Bo Tao +2 more | 2012-01-24 |
| 7993997 | Poly profile engineering to modulate spacer induced stress for device enhancement | Vincent Ho, Wenhe Lin, Young Way Teh, Yong Kong Siew, Bei Chao Zhang +2 more | 2011-08-09 |
| 7803704 | Reliable interconnects | Bei Chao Zhang, Chim Seng Seet, Fan Zhang, Yong Chiang EE, Bo Tao +2 more | 2010-09-28 |
| 7749894 | Integrated circuit processing system | Xianbin Wang, Liang-Choo Hsia, Teck Jung Tang, Huang Liu | 2010-07-06 |
| 7372156 | Method to fabricate aligned dual damascene openings | Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Alan Cuthbertson +1 more | 2008-05-13 |
| 7276440 | Method of fabrication of a die oxide ring | Fan Zhang, Bei Chao Zhang, Wuping Liu, Kho Liep Chok, Liang-Choo Hsia +2 more | 2007-10-02 |
| 6995087 | Integrated circuit with simultaneous fabrication of dual damascene via and trench | Wuping Liu, Bei Chao Zhang, Alan Cuthbertson | 2006-02-07 |
| 6967156 | Method to fabricate aligned dual damascene openings | Yeow Kheng Lim, Wuping Liu, Tae Jong Lee, Bei Chao Zhang, Alan Cuthbertson +1 more | 2005-11-22 |
| 6586143 | Accurate wafer patterning method for mass production | Tak Yan Tse, Sajan Marokkey Raphael, Fang Hong Gn | 2003-07-01 |
| 6528886 | Intermetal dielectric layer for integrated circuits | Huang Liu, John Sudijono, Edwin Goh, Alan Cuthbertson, Arthur Ang +3 more | 2003-03-04 |
| 6451687 | Intermetal dielectric layer for integrated circuits | Huang Liu, John Sudijono, Edwin Goh, Alan Cuthbertson, Arthur Ang +3 more | 2002-09-17 |
| 6403478 | Low pre-heat pressure CVD TiN process | Chim Seng Seet, Chyi S. Chern | 2002-06-11 |
| 6352904 | Alignment mark strategy for oxide CMP | Soon Ee Neoh | 2002-03-05 |
| 6235437 | Multi-segment global alignment mark | Soon Ee Neoh, Zadig Cheung-Ching Lam, Kay Chai Ang | 2001-05-22 |
| 6184104 | Alignment mark strategy for oxide CMP | Soon Ee Neoh | 2001-02-06 |
| 6146969 | Printing optimized global alignment mark at contact/via layers | Soon Ee Neoh, Phuan Yee Hwee | 2000-11-14 |
| 6054361 | Preserving the zero mark for wafer alignment | Zuo Ya Yang, Tsun-Lung Alex Cheng | 2000-04-25 |
| 6022649 | Wafer stepper method utilizing a multi-segment global alignment mark | Soon Ee Neoh, Zadig Cheung-Ching Lam, Kay Chai Ang | 2000-02-08 |