Issued Patents All Time
Showing 101–125 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7759207 | Integrated circuit system employing stress memorization transfer | Pradeep Ramachandramurthy Yelehanka | 2010-07-20 |
| 7727856 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Dong Kyun Sohn | 2010-06-01 |
| 7692213 | Integrated circuit system employing a condensation process | Lee-Wee Teo, Yung Fu Chong, Alain Chan | 2010-04-06 |
| 7592270 | Modulation of stress in stress film through ion implantation and its application in stress memorization technique | Lee-Wee Teo | 2009-09-22 |
| 7285804 | Thyristor-based SRAM | Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Weining Li | 2007-10-23 |
| 7169675 | Material architecture for the fabrication of low temperature transistor | Chung Foong Tan, Jinping Liu, Hyeokjae Lee, Kheng Chok Tee | 2007-01-30 |
| 7148522 | Thyristor-based SRAM | Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai, Weining Li | 2006-12-12 |
| 7071069 | Shallow amorphizing implant for gettering of deep secondary end of range defects | Chung Foong Tan, Hyeokjae Lee, Eng Fong Chor | 2006-07-04 |
| 6969646 | Method of activating polysilicon gate structure dopants after offset spacer deposition | Francis Benistant | 2005-11-29 |
| 6946349 | Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses | Jae Gon Lee, Hwa Weng Koh, Dong Kyun Sohn | 2005-09-20 |
| 6924180 | Method of forming a pocket implant region after formation of composite insulator spacers | — | 2005-08-02 |
| 6897111 | Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory | Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Weining Li | 2005-05-24 |
| 6849481 | Thyristor-based SRAM and method for the fabrication thereof | Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Tommy Lai, Weining Li | 2005-02-01 |
| 6841441 | Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2005-01-11 |
| 6828082 | Method to pattern small features by using a re-flowable hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2004-12-07 |
| 6815355 | Method of integrating L-shaped spacers in a high performance CMOS process via use of an oxide-nitride-doped oxide spacer | — | 2004-11-09 |
| 6747314 | Method to form a self-aligned CMOS inverter using vertical device integration | Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy +2 more | 2004-06-08 |
| 6709934 | Method for forming variable-K gate dielectric | James Yong Meng Lee, Ying-Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan +2 more | 2004-03-23 |
| 6664153 | Method to fabricate a single gate with dual work-functions | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2003-12-16 |
| 6632712 | Method of fabricating variable length vertical transistors | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2003-10-14 |
| 6610575 | Forming dual gate oxide thickness on vertical transistors by ion implantation | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6610604 | Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask | Chew Hoe Ang, Eng Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou +1 more | 2003-08-26 |
| 6605501 | Method of fabricating CMOS device with dual gate electrode | Chew Hoe Ang, Eng Hua Lim, Cher Liang Cha, Jia Zhen Zheng, Mei Sheng Zhou | 2003-08-12 |
| 6566208 | Method to form elevated source/drain using poly spacer | Yang Pan, Lee Yong Meng, Leung Keung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng +2 more | 2003-05-20 |
| 6544824 | Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel | Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Ravi Sundaresan, Yang Pan +2 more | 2003-04-08 |