Issued Patents All Time
Showing 76–100 of 152 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8633081 | Modifying growth rate of a device layer | Chunshan Yin, Palanivel Balasubramaniam, Jae Gon Lee | 2014-01-21 |
| 8536558 | RRAM structure with improved memory margin | Shyue Seng Tan, Eng Huat Toh | 2013-09-17 |
| 8530310 | Memory cell with improved retention | Lee-Wee Teo, Chunshan Yin, Shyue Seng Tan, Chung Foong Tan, Jae Gon Lee +1 more | 2013-09-10 |
| 8502279 | Nano-electro-mechanical system (NEMS) structures with actuatable semiconductor fin on bulk substrates | Eng Huat Toh, Chung Foong Tan | 2013-08-06 |
| 8492235 | FinFET with stressors | Eng Huat Toh, Jae Gon Lee, Chung Foong Tan | 2013-07-23 |
| 8470700 | Semiconductor device with reduced contact resistance and method of manufacturing thereof | Eng Huat Toh, Jae Gon Lee, Chung Foong Tan, Shiang Yang Ong | 2013-06-25 |
| 8446779 | Non-volatile memory using pyramidal nanocrystals as electron storage elements | Chunshan Yin, Shyue Seng Tan, Jae Gon Lee, Chung Foong Tan | 2013-05-21 |
| 8440533 | Self-aligned contact for replacement metal gate and silicide last processes | Eng Huat Toh | 2013-05-14 |
| 8368127 | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current | Ming Zhu, Shyue Seng Tan, Eng Huat Toh | 2013-02-05 |
| 8324031 | Diffusion barrier and method of formation thereof | Shyue Seng Tan, Lee-Wee Teo, Yung Fu Chong, Sanford Chu | 2012-12-04 |
| 8288800 | Hybrid transistor | Ming Zhu, Chun Shan Yin, Shyue Seng Tan | 2012-10-16 |
| 8236646 | Non-volatile memory manufacturing method using STI trench implantation | Tze Ho Simon Chan, Weining Li, Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Tommy Lai | 2012-08-07 |
| 8153537 | Method for fabricating semiconductor devices using stress engineering | Sai-Hooi Yeong, Tao Wang, Shesh Mani Pandey, Chia Ching Yeo, Ying-Keung Leung | 2012-04-10 |
| 8119541 | Modulation of stress in stress film through ion implantation and its application in stress memorization technique | Lee-Wee Teo | 2012-02-21 |
| 8008744 | Selective STI stress relaxation through ion implantation | Lee-Wee Teo, Shiang Yang Ong, Jae Gon Lee, Vincent Leong, Dong Kyun Sohn | 2011-08-30 |
| 7998835 | Strain-direct-on-insulator (SDOI) substrate and method of forming | Lee-Wee Teo, Chung Foong Tan, Shyue Seng Tan | 2011-08-16 |
| 7994010 | Process for fabricating a semiconductor device having embedded epitaxial regions | Lee-Wee Teo, Alain Chan, Chung Foong Tan | 2011-08-09 |
| 7964894 | Integrated circuit system employing stress memorization transfer | Pradeep Ramachandramurthy Yelehanka | 2011-06-21 |
| 7935589 | Enhanced stress for transistors | Lee-Wee Teo, Jae Gon Lee, Shyue Seng Tan | 2011-05-03 |
| 7888214 | Selective stress relaxation of contact etch stop layer through layout design | Lee-Wee Teo, Dong Kyun Sohn | 2011-02-15 |
| 7867835 | Integrated circuit system for suppressing short channel effects | Jae Gon Lee, Young Way Teh, Wenzhi Gao | 2011-01-11 |
| 7846800 | Avoiding plasma charging in integrated circuits | Chung Foong Tan, Jae Gon Lee, Lee-Wee Teo, Chunshan Yin | 2010-12-07 |
| 7833888 | Integrated circuit system employing grain size enlargement | Chung Foong Tan, Jae Gon Lee, Lee-Wee Teo | 2010-11-16 |
| 7816274 | Methods for normalizing strain in a semiconductor device | Lee-Wee Teo, Chung Foong Tan, Alain Chan | 2010-10-19 |
| 7795104 | Method for fabricating device structures having a variation in electrical conductivity | Lee-Wee Teo, Shyue Seng Tan | 2010-09-14 |