Issued Patents All Time
Showing 26–50 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9627378 | Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding | Takashi Ando, Robert H. Dennard, Isaac Lauer, Ghavam G. Shahidi | 2017-04-18 |
| 9564500 | Fully-depleted SOI MOSFET with U-shaped channel | Takashi Ando, Robert H. Dennard, Isaac Lauer | 2017-02-07 |
| 9471884 | Multi-model blending | Hendrik F. Hamann, Youngdeok Hwang, Theodore G. van Kessel, Ildar Khabibrakhmanov, Siyuan Lu | 2016-10-18 |
| 9287136 | FinFET field-effect transistors with atomic layer doping | Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Dae-Gyu Park, Xinhui Wang +1 more | 2016-03-15 |
| 9201041 | Extended gate sensor for pH sensing | Timothy J. Dalton, Ashish Jagtiani, Sufi Zafar | 2015-12-01 |
| 9171844 | Gate structures and methods of manufacture | Unoh Kwon, Viorel Ontalus | 2015-10-27 |
| 9070686 | Wiring switch designs based on a field effect device for reconfigurable interconnect paths | Daniel C. Edelstein, Stephen M. Gates, Thomas Theis | 2015-06-30 |
| 9048261 | Fabrication of field-effect transistors with atomic layer doping | Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Dae-Gyu Park, Xinhui Wang +1 more | 2015-06-02 |
| 8993395 | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | Dureseti Chidambarrao, Philip J. Oldiges, Viorel Ontalus | 2015-03-31 |
| 8921939 | Stressed channel FET with source/drain buffers | Jeffrey B. Johnson, Philip J. Oldiges, Viorel Ontalus, Kai Xiu | 2014-12-30 |
| 8895384 | Gate structures and methods of manufacture | Unoh Kwon, Viorel Ontalus | 2014-11-25 |
| 8860095 | Interconnect wiring switches and integrated circuits including the same | Stephen M. Gates, Daniel C. Edelstein, Kailash Gopalakrishnan | 2014-10-14 |
| 8815684 | Bulk finFET with super steep retrograde well | Jin Cai, Kevin K. Chan, Robert H. Dennard, Bruce B. Doris, Barry P. Linder +1 more | 2014-08-26 |
| 8809872 | Bulk finFET with super steep retrograde well | Jin Cai, Kevin K. Chan, Robert H. Dannard, Bruce B. Doris, Barry P. Linder | 2014-08-19 |
| 8803217 | Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode | Rajesh A. Rao | 2014-08-12 |
| 8575588 | Phase change memory cell with heater and method therefor | Leo Mathew, Dharmesh Jawarani, Tushar P. Merchant | 2013-11-05 |
| 8563355 | Method of making a phase change memory cell having a silicide heater in conjunction with a FinFET | Leo Mathew, Tushar P. Merchant, Rajesh A. Rao | 2013-10-22 |
| 8541814 | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | Dureseti Chidambarrao, Philip J. Oldiges, Viorel Ontalus | 2013-09-24 |
| 8525169 | Reliable physical unclonable function for device authentication | Daniel C. Edelstein, Stephen M. Gates, Edward W. Kiewra, Satyanarayana V. Nitta, Dirk Pfeiffer | 2013-09-03 |
| 8373221 | Nanocluster charge storage device | Robert F. Steimle, Bruce E. White | 2013-02-12 |
| 8361847 | Stressed channel FET with source/drain buffers | Jeffrey B. Johnson, Philip J. Oldiges, Viorel Ontalus, Kai Xiu | 2013-01-29 |
| 8354313 | Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures | Unoh Kwon, Dechao Guo, Siddarth A. Krishnan | 2013-01-15 |
| 8349684 | Semiconductor device with high K dielectric control terminal spacer structure | Jin Cai, Amlan Majumdar, Ghavam G. Shahidi | 2013-01-08 |
| 8097873 | Phase change memory structures | Tushar P. Merchant, Rajesh A. Rao | 2012-01-17 |
| 8043888 | Phase change memory cell with heater and method therefor | Leo Mathew, Dharmesh Jawarani, Tushar P. Merchant | 2011-10-25 |