Issued Patents All Time
Showing 76–100 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7241695 | Semiconductor device having nano-pillars and method therefor | Leo Mathew, Rajesh A. Rao | 2007-07-10 |
| 7195983 | Programming, erasing, and reading structure for an NVM cell | Gowrishankar L. Chindalore, James D. Burnett, Craig T. Swift | 2007-03-27 |
| 7192876 | Transistor with independent gate structures | Leo Mathew, Robert F. Steimle | 2007-03-20 |
| 7186616 | Method of removing nanoclusters in a semiconductor device | Rajesh A. Rao, Robert F. Steimle | 2007-03-06 |
| 7160775 | Method of discharging a semiconductor device | Erwin J. Prinz, Rajesh A. Rao, Michael A. Sadd, Robert F. Steimle, Craig T. Swift +1 more | 2007-01-09 |
| 7109550 | Semiconductor fabrication process with asymmetrical conductive spacers | Leo Mathew | 2006-09-19 |
| 7105395 | Programming and erasing structure for an NVM cell | James D. Burnett, Gowrishankar L. Chindalore, Craig T. Swift | 2006-09-12 |
| 7098502 | Transistor having three electrically isolated electrodes and method of formation | Leo Mathew | 2006-08-29 |
| 7091130 | Method of forming a nanocluster charge storage device | Rajesh A. Rao, Robert F. Steimle, Gowrishankar L. Chindalore | 2006-08-15 |
| 7018876 | Transistor with vertical dielectric structure | Leo Mathew | 2006-03-28 |
| 6991984 | Method for forming a memory structure using a modified surface topography and structure thereof | Paul A. Ingersoll, Gowrishankar L. Chindalore | 2006-01-31 |
| 6967143 | Semiconductor fabrication process with asymmetrical conductive spacers | Leo Mathew | 2005-11-22 |
| 6964902 | Method for removing nanoclusters from selected regions | Robert F. Steimle, Jane A. Yater, Gowrishankar L. Chindalore, Craig T. Swift, Steven G. H. Anderson | 2005-11-15 |
| 6958265 | Semiconductor device with nanoclusters | Robert F. Steimle, Wayne M. Paulson, Rajesh A. Rao, Bruce E. White, Erwin J. Prinz | 2005-10-25 |
| 6903967 | Memory with charge storage locations and adjacent gate structures | Leo Mathew, Robert F. Steimle | 2005-06-07 |
| 6831310 | Integrated circuit having multiple memory types and method of formation | Leo Mathew | 2004-12-14 |
| 6808986 | Method of forming nanocrystals in a memory device | Rajesh A. Rao, Tushar P. Merchant | 2004-10-26 |
| 6784103 | Method of formation of nanocrystals on a semiconductor structure | Rajesh A. Rao, Tushar P. Merchant | 2004-08-31 |
| 6583057 | Method of forming a semiconductor device having a layer deposited by varying flow of reactants | Prasad Alluri | 2003-06-24 |
| 6413819 | Memory device and method for using prefabricated isolated storage elements | Sufi Zafar, Bich-Yen Nguyen, Sucharita Madhukar, Daniel T. Pham, Michael A. Sadd +1 more | 2002-07-02 |
| 6350690 | Process for achieving full global planarization during CMP of damascene semiconductor structures | Gary Paul Schwartz, Stephen W. Hymes | 2002-02-26 |
| 6344403 | Memory device and method for manufacture | Sucharita Madhukar, David L. O'Meara, Kristen C. Smith, Bich-Yen Nguyen | 2002-02-05 |
| 6330184 | Method of operating a semiconductor device | Bruce E. White, Bo Jiang | 2001-12-11 |
| 6320784 | Memory cell and method for programming thereof | Sucharita Madhukar, Bo Jiang, Bruce E. White, Srikanth B. Samavedam, David L. O'Meara +1 more | 2001-11-20 |
| 6307782 | Process for operating a semiconductor device | Michael A. Sadd, Bruce E. White | 2001-10-23 |