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USPTO Patent Rankings Data through Dec 31, 2025
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Daniel J. Vitkavage — 14 Patents

ATAT&T: 6 patents #3,060 of 18,772Top 20%
AGAgere Systems Guardian: 4 patents #47 of 810Top 6%
ASAgere Systems: 3 patents #475 of 1,849Top 30%
RIResearch Triangle Institute: 1 patents #166 of 344Top 50%
Emmaus, PA: #43 of 365 inventorsTop 15%
Pennsylvania: #5,450 of 74,527 inventorsTop 8%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Daniel J. Vitkavage has been granted 14 US patents while listed as an inventor at AT&T. The first was granted in 1991 and the most recent in June 2004. Daniel J. Vitkavage ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Daniel J. Vitkavage in Emmaus, PA, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6750495 Damascene capacitors for integrated circuits Glenn B. Alers, Tseng-Chung Lee, Helen L. Maynard 2004-06-15
6680542 Damascene structure having a metal-oxide-metal capacitor associated therewith Gerald W. Gibson, Richard W. Gregor, Chun-Yung Sung, Allen Yen 2004-01-20
6555910 Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof Robert A. Ashton, Steven Alan Lytle, Mary Roby, Morgan J. Thoma 2003-04-29
6384446 Grooved capacitor structure for integrated circuits Kuo-Hua Lee, Simon John Molloy 2002-05-07 $7,081,000
6362638 Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies Robert A. Ashton, Steven Alan Lytle, Mary Roby 2002-03-26 $3,860,000
6329281 Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer Steven Alan Lytle, Mary Roby 2001-12-11 $9,471,000
6280644 Method of planarizing a surface on an integrated circuit Edward P. Martin, Jr., Morgan J. Thoma 2001-08-28 $4,758,000
6046115 Method for removing etching residues and contaminants Simon John Molloy 2000-04-04 $118,100,000
6028359 Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor Sailesh Mansinh Merchant, Susan Clay Vitkavage 2000-02-22 $68,300,000
5858873 Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof Susan Clay Vitkavage, Sailesh Mansinh Merchant 1999-01-12 $118,358,000
5849639 Method for removing etching residues and contaminants Simon John Molloy 1998-12-15 $75,651,000
5200358 Integrated circuit with planar dielectric layer Cheryl Anne Bollinger, Min-Liang Chen, David P. Favreau, Kurt G. Steiner 1993-04-06
5168330 Semiconductor device having a semiconductor substrate interfaced to a dissimilar material by means of a single crystal pseudomorphic interlayer Gaius Gillman Fountain, Jr., Sunil Hattangady, Ronald A. Rudder, Robert J. Markunas 1992-12-01
5022958 Method of etching for integrated circuits with planarized dielectric David P. Favreau, Jane A. Swiderski 1991-06-11