Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6973637 | Process for the selective control of feature size in lithographic processing | John Sharpe, Jerome Chu, Matthew Moucheron | 2005-12-06 |
| 6555910 | Use of small openings in large topography features to improve dielectric thickness control and a method of manufacture thereof | Robert A. Ashton, Steven Alan Lytle, Morgan J. Thoma, Daniel J. Vitkavage | 2003-04-29 |
| 6362638 | Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies | Robert A. Ashton, Steven Alan Lytle, Daniel J. Vitkavage | 2002-03-26 |
| 6329281 | Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer | Steven Alan Lytle, Daniel J. Vitkavage | 2001-12-11 |