Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7151059 | MOS transistor and method of manufacture | Samir Chaudhry, Sidhartha Sen, Sundar Srinivasan Chetlur, Pradip K. Roy | 2006-12-19 |
| 6847077 | Capacitor for a semiconductor device and method for fabrication therefor | Sylvia Thomas, Michael Jay Parrish, Tony Ivanov, Edward B. Harris, Michael Carroll | 2005-01-25 |
| 6740912 | Semiconductor device free of LLD regions | Samir Chaudhry, Sidharta Sen, Sundar Srinivasan Chetlur, Pradip K. Roy | 2004-05-25 |
| 6680542 | Damascene structure having a metal-oxide-metal capacitor associated therewith | Gerald W. Gibson, Chun-Yung Sung, Daniel J. Vitkavage, Allen Yen | 2004-01-20 |
| 6359339 | Multi-layered metal silicide resistor for Si Ic's | Isik C. Kizilyalli, Sailesh Mansinh Merchant, Jaseph R. Radosevich, Pradip K. Roy | 2002-03-19 |
| 6252270 | Increased cycle specification for floating-gate and method of manufacture thereof | Isik C. Kizilyalli, Ranbir Singh | 2001-06-26 |
| 6023093 | Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof | Isik C. Kizilyalli | 2000-02-08 |
| 6008091 | Floating gate avalanche injection MOS transistors with high K dielectric control gates | Isik C. Kizilyalli, Pradip K. Roy | 1999-12-28 |
| 5843827 | Method of reducing dielectric damage from plasma etch charging | Chung Wai Leung | 1998-12-01 |
| 5312781 | Flash EEPROM fabrication process that uses a selective wet chemical etch | Chung Wai Leung | 1994-05-17 |
| 5110756 | Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density | Chung Wai Leung | 1992-05-05 |