Issued Patents All Time
Showing 76–100 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5688717 | Construction that prevents the undercut of interconnect lines in plasma metal etch systems | Lewis Shen, Sheshadri Ramaswami, Mark S. Chang | 1997-11-18 |
| 5679608 | Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC | Mark S. Chang | 1997-10-21 |
| 5674781 | Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application | Richard J. Huang, Rajat Rakkhit, Raymond T. Lee | 1997-10-07 |
| 5675186 | Construction that prevents the undercut of interconnect lines in plasma metal etch systems | Lewis Shen, Sheshadri Ramaswami, Mark S. Chang | 1997-10-07 |
| 5670828 | Tunneling technology for reducing intra-conductive layer capacitance | Simon S. Chan, Richard J. Huang | 1997-09-23 |
| 5665641 | Method to prevent formation of defects during multilayer interconnect processing | Lewis Shen | 1997-09-09 |
| 5654589 | Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application | Richard J. Huang, Rajat Rakkhit, Raymond T. Lee | 1997-08-05 |
| 5646448 | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Steven C. Avanzino, Scott Luning, Bryan Tracy +2 more | 1997-07-08 |
| 5639691 | Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device | Richard K. Klein, Darrell M. Erb, Steven C. Avanzino, Scott Luning, Bryan Tracy +2 more | 1997-06-17 |
| 5635423 | Simplified dual damascene process for multi-level metallization and interconnection structure | Richard J. Huang, Angela T. Hui, Mark S. Chang, Ming-Ren Lin | 1997-06-03 |
| 5625231 | Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology | Richard J. Huang | 1997-04-29 |
| 5559055 | Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance | Mark S. Chang | 1996-09-24 |
| 5550405 | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS | Mark S. Chang | 1996-08-27 |
| 5539247 | Selective metal via plug growth technology for deep sub-micrometer ULSI | Seshadri Ramaswami, David F. Kyser | 1996-07-23 |
| 5534731 | Layered low dielectric constant technology | — | 1996-07-09 |
| 5471093 | Pseudo-low dielectric constant technology | — | 1995-11-28 |
| 5453402 | Selective metal via plug growth technology for deep sub-micrometer ULSI | Seshadri Ramaswami, David F. Kyser | 1995-09-26 |
| 5451545 | Process for forming stable local interconnect/active area silicide structure VLSI applications | Seshadri Ramaswami | 1995-09-19 |
| 5365111 | Stable local interconnect/active area silicide structure for VLSI applications | Seshadri Ramaswami | 1994-11-15 |
| 4892844 | Making a low resistance three layered contact for silicon devices | Bernard W. K. Ho, Hsiang-Wen Chen, Hugo W. K. Chan | 1990-01-09 |
| 4871962 | Method for measuring the size of vias | — | 1989-10-03 |
| 4796081 | Low resistance metal contact for silicon devices | Bernard W. K. Ho, Hsiang-Wen Chen, Hugo W. K. Chan | 1989-01-03 |
| 4762805 | Nitride-less process for VLSI circuit device isolation | Hugo W. K. Chan | 1988-08-09 |
| 4744056 | Stable high density RAM | James Yu, Hong-Gee Fang, Moon-Yee Wang | 1988-05-10 |
| 4727045 | Plugged poly silicon resistor load for static random access memory cells | Hugo W. K. Chan | 1988-02-23 |