Issued Patents 2021
Showing 51–75 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11038104 | Resistive memory crossbar array with top electrode inner spacers | Hiroyuki Miyazoe, Iqbal Rashid Saraf, Shyng-Tsong Chen | 2021-06-15 |
| 11038103 | Tightly integrated 1T1R ReRAM for planar technology | Alexander Reznicek, Pouya Hashemi | 2021-06-15 |
| 11037986 | Stacked resistive memory with individual switch control | Jingyun Zhang, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee | 2021-06-15 |
| 11037832 | Threshold voltage adjustment by inner spacer material selection | Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2021-06-15 |
| 11024724 | Vertical FET with differential top spacer | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi | 2021-06-01 |
| 11024740 | Asymmetric channel threshold voltage | Choonghyun Lee, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi | 2021-06-01 |
| 11018192 | Reduction of metal resistance in vertical ReRAM cells | Pouya Hashemi, Choonghyun Lee | 2021-05-25 |
| 11018062 | Multivalent oxide cap for multiple work function gate stacks on high mobility channel materials | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi | 2021-05-25 |
| 11011704 | Forming RRAM cell structure with filament confinement | Juntao Li, Dexin Kong, Kangguo Cheng | 2021-05-18 |
| 11004511 | Memory device having separate programming and resistance readout control | Guy M. Cohen, Nanbo Gong | 2021-05-11 |
| 10991881 | Method for controlling the forming voltage in resistive random access memory devices | Steven P. Consiglio, Cory Wajda, Kandabara Tapily, Takaaki Tsunomura, Paul C. Jamison +3 more | 2021-04-27 |
| 10991763 | Vertical array of resistive switching devices having restricted filament regions and tunable top electrode volume | Robert L. Bruce, Hiroyuki Miyazoe, John Rozen | 2021-04-27 |
| 10985069 | Gate stack optimization for wide and narrow nanosheet transistor devices | Jingyun Zhang, Choonghyun Lee | 2021-04-20 |
| 10978551 | Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor | Eduard A. Cartier, Hemanth Jagannathan, Paul C. Jamison, Vijay Narayanan | 2021-04-13 |
| 10971407 | Method of forming a complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate | Choonghyun Lee, Pouya Hashemi, Jingyun Zhang | 2021-04-06 |
| 10971593 | Oxygen reservoir for low threshold voltage P-type MOSFET | Choonghyun Lee, Jingyun Zhang | 2021-04-06 |
| 10971549 | Semiconductor memory device having a vertical active region | Juntao Li, Kangguo Cheng, Dexin Kong | 2021-04-06 |
| 10964603 | Hybrid gate stack integration for stacked vertical transport field-effect transistors | Tenko Yamashita, Oleg Gluschenkov, Chen Zhang, Koji Watanabe | 2021-03-30 |
| 10957937 | Three-terminal copper-driven neuromorphic device | Teodor K. Todorov, Vijay Narayanan, John Rozen | 2021-03-23 |
| 10957742 | Resistive random-access memory array with reduced switching resistance variability | Choonghyun Lee, Seyoung Kim, Wilfried E. Haensch | 2021-03-23 |
| 10950662 | Resistive memory device with meshed electrodes | Lawrence A. Clevenger, Chih-Chao Yang, Michael Rizzolo | 2021-03-16 |
| 10950787 | Method having resistive memory crossbar array employing selective barrier layer growth | Chih-Chao Yang, Lawrence A. Clevenger | 2021-03-16 |
| 10943924 | Semiconductor-on-insulator finFET devices with high thermal conductivity dielectrics | Choonghyun Lee, Sanghoon Shin | 2021-03-09 |
| 10943903 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Choonghyun Lee, Jingyun Zhang, Alexander Reznicek, Pouya Hashemi | 2021-03-09 |
| 10943787 | Confined work function material for gate-all around transistor devices | Jingyun Zhang, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi | 2021-03-09 |