Issued Patents 2016
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9502232 | Inhibiting diffusion of elements between material layers of a layered circuit structure | Sipeng Gu, Sandeep Gaan, Zhiguo Sun, Adam Selsley | 2016-11-22 |
| 9490129 | Integrated circuits having improved gate structures and methods for fabricating same | Xiang Hu | 2016-11-08 |
| 9478625 | Metal resistor using FinFET-based replacement gate process | Hui Zang, Min-hwa Chi | 2016-10-25 |
| 9466723 | Liner and cap layer for placeholder source/drain contact structure planarization and replacement | Haigou Huang, Qiang Fang, Jin Ping Liu | 2016-10-11 |
| 9455188 | Through silicon via device having low stress, thin film gaps and methods for forming the same | Sarasvathi Thangaraju, Chun Yu Wong | 2016-09-27 |
| 9455204 | 10 nm alternative N/P doped fin for SSRW scheme | Huy Cao, Jinping Liu, Guillaume Bouche | 2016-09-27 |
| 9443956 | Method for forming air gap structure using carbon-containing spacer | Hong Yu, Biao Zuo, Jin Ping Liu | 2016-09-13 |
| 9431528 | Lithographic stack excluding SiARC and method of using same | Hong Yu, Xiang Hu, Zhao Lun | 2016-08-30 |
| 9425127 | Method for forming an air gap around a through-silicon via | Hong Yu | 2016-08-23 |
| 9418832 | Method of forming a dielectric film | Hung-Wei Liu, Tsung-Liang Chen, Zhiguo Sun | 2016-08-16 |
| 9401416 | Method for reducing gate height variation due to overlapping masks | Hong Yu, Jin Ping Liu, Haigou Huang | 2016-07-26 |
| 9385192 | Shallow trench isolation integration methods and devices formed thereby | Hongliang Shen, Kyutae Na, Sandeep Gaan, Hsin-Neng Tai, Weihua Tong +6 more | 2016-07-05 |
| 9368342 | Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch | Haigou Huang, Jin Ping Liu | 2016-06-14 |
| 9349635 | Integrated circuits and methods of forming the same with multi-level electrical connection | San Leong Liew | 2016-05-24 |
| 9329471 | Achieving a critical dimension target based on resist characteristics | Guoxiang Ning, Xintuo Dai, Chin Teong Lim | 2016-05-03 |
| 9324841 | Methods for preventing oxidation damage during FinFET fabrication | Hong Yu, Hyucksoo Yang, Richard J. Carter | 2016-04-26 |
| 9318440 | Formation of carbon-rich contact liner material | Huy Cao, Songkram Srivathanakul, Garo Derderian, Boaz Alperson | 2016-04-19 |
| 9305832 | Dimension-controlled via formation processing | Xiang Hu, Yuping Ren, Duohui Bei, Sipeng Gu | 2016-04-05 |
| 9275898 | Method to improve selectivity cobalt cap process | Jiehui Shu, Zhiguo Sun, Yang Bum Lee | 2016-03-01 |
| 9230863 | Method for producing integrated circuit with smaller grains of tungsten | Jialin Yu, Jilin Xia, Girish Bohra | 2016-01-05 |
| 9230886 | Method for forming through silicon via with wafer backside protection | Lup San Leong, Zheng Zou, Alex See, Hai Cong, Xuesong Rao +1 more | 2016-01-05 |
| 9230822 | Uniform gate height for mixed-type non-planar semiconductor devices | Hong Yu, Haigou Huang, Jin Ping Liu | 2016-01-05 |