Issued Patents 2016
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524911 | Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device | Hao-Cheng Tsai, Yong Meng Lee | 2016-12-20 |
| 9508795 | Methods of fabricating nanowire structures | Chun Yu Wong, Ashish Baraskar, Jagar Singh | 2016-11-29 |
| 9502301 | Fabrication methods for multi-layer semiconductor structures | Suraj K. Patil | 2016-11-22 |
| 9490174 | Fabricating raised fins using ancillary fin structures | Xusheng Wu, Jianwei Peng | 2016-11-08 |
| 9478625 | Metal resistor using FinFET-based replacement gate process | Hui Zang, Huang Liu | 2016-10-25 |
| 9460996 | Integrated device with inductive and capacitive portions and fabrication methods | Hui Zang | 2016-10-04 |
| 9443771 | Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology | Yanping Shen, Ashish Jha, Haiting Wang | 2016-09-13 |
| 9425100 | Methods of facilitating fabricating transistors | Zhaoxu Shen, Haiting Wang, Qin Wang, Meixiong Zhao, Duohui Bei | 2016-08-23 |
| 9418899 | Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology | Yan Ping SHEN, Xusheng Wu, Weihua Tong, Haiting Wang | 2016-08-16 |
| 9419015 | Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device | Xusheng Wu, Changyong Xiao | 2016-08-16 |
| 9396995 | MOL contact metallization scheme for improved yield and device reliability | Suraj K. Patil, Garo Derderian, Wen-Pin Peng | 2016-07-19 |
| 9385126 | Silicon-on-insulator finFET with bulk source and drain | Yanxiang Liu | 2016-07-05 |
| 9385124 | Methods of forming reduced thickness spacers in CMOS based integrated circuit products | Wen-Pin Peng, Garo Derderian | 2016-07-05 |
| 9379209 | Selectively forming a protective conductive cap on a metal gate electrode | Xiuyu Cai, Jiajun Mao, Xusheng Wu | 2016-06-28 |
| 9379186 | Fet structure for minimum size length/width devices for performance boost and mismatch reduction | Qin Wang, Meixiong Zhao, Zhaoxu Shen, Haiting Wang, Lucas M. Salazar +1 more | 2016-06-28 |
| 9362277 | FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming | Ajey Poovannummoottil Jacob, Abhijeet Paul | 2016-06-07 |
| 9337340 | FinFET with active region shaped structures and channel separation | Hoong Shing Wong | 2016-05-10 |
| 9337324 | Bipolar transistor, band-gap reference circuit and virtual ground reference circuit | Lihying Ching, Deyuan Xiao | 2016-05-10 |
| 9331159 | Fabricating transistor(s) with raised active regions having angled upper surfaces | Ashish Jha, Yan Ping SHEN, Wei Tong, Haiting Wang | 2016-05-03 |
| 9312145 | Conformal nitridation of one or more fin-type transistor layers | Wei Tong, Tien Ying Luo, Yan Ping SHEN, Feng Zhou, Jun Lian +4 more | 2016-04-12 |
| 9299608 | T-shaped contacts for semiconductor device | Xusheng Wu, Changyong Xiao | 2016-03-29 |
| 9263587 | Fin device with blocking layer in channel region | Ajey Poovannummoottil Jacob | 2016-02-16 |
| 9252272 | FinFET semiconductor device having local buried oxide | Yanxiang Liu | 2016-02-02 |