Issued Patents 2016
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9478622 | Wrap-around contact for finFET | Jinping Liu | 2016-10-25 |
| 9455198 | Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices | Hongliang Shen, Zhenyu Hu, Lun Zhao, Richard J. Carter, Xusheng Wu | 2016-09-27 |
| 9443956 | Method for forming air gap structure using carbon-containing spacer | Biao Zuo, Jin Ping Liu, Huang Liu | 2016-09-13 |
| 9431528 | Lithographic stack excluding SiARC and method of using same | Xiang Hu, Zhao Lun, Huang Liu | 2016-08-30 |
| 9425127 | Method for forming an air gap around a through-silicon via | Huang Liu | 2016-08-23 |
| 9419101 | Multi-layer spacer used in finFET | Jianwei Peng, Zhao Lun, Tao Han, Hsien-Ching Lo, Basab Banerjee +2 more | 2016-08-16 |
| 9406676 | Method for forming single diffusion breaks between finFET devices and the resulting devices | Hongliang Shen, Zhenyu Hu, Jin Ping Liu | 2016-08-02 |
| 9401416 | Method for reducing gate height variation due to overlapping masks | Jin Ping Liu, Haigou Huang, Huang Liu | 2016-07-26 |
| 9368496 | Method for uniform recess depth and fill in single diffusion break for fin-type process and resulting devices | Hongliang Shen | 2016-06-14 |
| 9362176 | Uniform exposed raised structures for non-planar semiconductor devices | Hongliang Shen, Zhao Lun, Zhenyu Hu, Richard J. Carter | 2016-06-07 |
| 9356147 | FinFET spacer etch for eSiGe improvement | Hyucksoo Yang, Puneet Khanna | 2016-05-31 |
| 9337306 | Multi-phase source/drain/gate spacer-epi formation | Jianwei Peng, Xusheng Wu, Zhao Lun | 2016-05-10 |
| 9324713 | Eliminating field oxide loss prior to FinFET source/drain epitaxial growth | Bingwu Liu, Hui Zang, Lun Zhao | 2016-04-26 |
| 9324841 | Methods for preventing oxidation damage during FinFET fabrication | Hyucksoo Yang, Huang Liu, Richard J. Carter | 2016-04-26 |
| 9236312 | Preventing EPI damage for cap nitride strip scheme in a Fin-shaped field effect transistor (FinFET) device | Hyucksoo Yang, Richard J. Carter | 2016-01-12 |
| 9230822 | Uniform gate height for mixed-type non-planar semiconductor devices | Haigou Huang, Jin Ping Liu, Huang Liu | 2016-01-05 |