Issued Patents 2003
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670667 | Asymmetric gates for high density DRAM | Wayne F. Ellis, Jack A. Mandelman, Mary E. Weybright | 2003-12-30 |
| 6660581 | Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices | Haining Yang | 2003-12-09 |
| 6656817 | Method of filling isolation trenches in a substrate | Laertis Economikos, Byeong Y. Kim | 2003-12-02 |
| 6642566 | Asymmetric inside spacer for vertical transistor | Jack A. Mandelman, Haining Yang | 2003-11-04 |
| 6638815 | Formation of self-aligned vertical connector | Gary B. Bronner | 2003-10-28 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Carl Radens, Ulrike Gruening | 2003-10-07 |
| 6596592 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Russell J. Houghton, Jack A. Mandelman, William R. Tonti | 2003-07-22 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | James W. Adkisson, Jeffrey P. Gambino, Jack A. Mandelman | 2003-07-08 |
| 6579759 | Formation of self-aligned buried strap connector | Michael P. Chudzik, Jochen Beintner, Rajarao Jammy | 2003-06-17 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Dureseti Chidambarrao, Jack A. Mandelman, Kevin McStay | 2003-06-03 |
| 6573137 | Single sided buried strap | Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening, Stephan Kudelka +5 more | 2003-06-03 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Carl Radens, Gary B. Bronner | 2003-05-27 |
| 6566219 | Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening | Gerhard Kunkel, Shahid Butt, Armin Reith, Munir D. Naeem | 2003-05-20 |
| 6548357 | Modified gate processing for optimized definition of array and logic devices on same chip | Mary E. Weybright, Gary B. Bronner, Richard A. Conti, Jeffrey P. Gambino, Peter D. Hoh +1 more | 2003-04-15 |
| 6541810 | Modified vertical MOSFET and methods of formation thereof | Prakash Dev, Rajeev Malik, Larry Nesbit | 2003-04-01 |
| 6518641 | Deep slit isolation with controlled void | Jack A. Mandelman, Johnathan E. Faltermeier, William R. Tonti | 2003-02-11 |
| 6518118 | Structure and process for buried bitline and single sided buried conductor formation | Satish D. Athavale, Jack A. Mandelman | 2003-02-11 |
| 6509226 | Process for protecting array top oxide | Venkatachalam C. Jaiprakash, Jack A. Mandelman, Rajeev Malik, Mihel Seitz | 2003-01-21 |
| 6504210 | Fully encapsulated damascene gates for Gigabit DRAMs | Jeffrey P. Gambino, Jack A. Mandelman, Viraj Y. Sardesai, Mary E. Weybright | 2003-01-07 |
| 6503798 | Low resistance strap for high density trench DRAMS | Jeffrey P. Gambino, Herbert L. Ho, Akira Sudo | 2003-01-07 |