Issued Patents 2003
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6649935 | Self-aligned, planarized thin-film transistors, devices employing the same | Louis L. Hsu, Jack A. Mandelman, Li-Kong Wang | 2003-11-18 |
| 6646949 | Word line driver for dynamic random access memories | Wayne F. Ellis, Louis L. Hsu, Jack A. Mandelman | 2003-11-11 |
| 6642584 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, Yujun Li | 2003-11-04 |
| 6635543 | SOI hybrid structure with selective epitaxial growth of silicon | Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park | 2003-10-21 |
| 6633055 | Electronic fuse structure and method of manufacturing | Claude L. Bertin, Erik L. Hedberg, Max G. Levy, Timothy D. Sullivan | 2003-10-14 |
| 6624031 | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure | Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more | 2003-09-23 |
| 6621324 | Redundant antifuse segments for improved programming efficiency | John A. Fifield | 2003-09-16 |
| 6611050 | Chip edge interconnect apparatus and method | Thomas G. Ference, Wayne J. Howell, Richard Q. Williams | 2003-08-26 |
| 6596592 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman | 2003-07-22 |
| 6590258 | SIO stacked DRAM logic | Ramachandra Divakauni, Mark C. Hakey, William H. Ma, Jack A. Mandclman | 2003-07-08 |
| 6580650 | DRAM word line voltage control to insure full cell writeback level | Wayne F. Ellis, Russell J. Houghton, Mark D. Jacunski, Thomas M. Maffitt | 2003-06-17 |
| 6577156 | Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox | Darren L. Anand, John E. Barth, Jr., John A. Fifield, Pamela S. Gillis, Peter O. Jakobsen +4 more | 2003-06-10 |
| 6574763 | Method and apparatus for semiconductor integrated circuit testing and burn-in | Claude L. Bertin, Erik L. Hedberg, Russell J. Houghton | 2003-06-03 |
| 6570207 | Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex | Louis L. Hsu, Jack A. Mandelman, Carl Radens | 2003-05-27 |
| 6566191 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Carl Radens, Richard Strub | 2003-05-20 |
| 6563736 | Flash memory structure having double celled elements and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Jack A. Mandelman | 2003-05-13 |
| 6555891 | SOI hybrid structure with selective epitaxial growth of silicon | Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park | 2003-04-29 |
| 6544837 | SOI stacked DRAM logic | Ramachandra Divakauni, Mark C. Hakey, William H. Ma, Jack A. Mandelman | 2003-04-08 |
| 6541837 | Charge-coupled device wafer cover plate with compact interconnect wiring | Claude L. Bertin, Albert Kao, Jerzy M. Zalesinski | 2003-04-01 |
| 6538295 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, Carl Radens | 2003-03-25 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, Anthony J. Dally, John A. Fifield, John Jesse Higgins, Jack A. Mandelman +1 more | 2003-03-11 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain | Qiuyi Ye, Yujun Li, Jack A. Mandelman | 2003-03-04 |
| 6518641 | Deep slit isolation with controlled void | Jack A. Mandelman, Ramachandra Divakaruni, Johnathan E. Faltermeier | 2003-02-11 |