Issued Patents 2003
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670667 | Asymmetric gates for high density DRAM | Ramachandra Divakaruni, Wayne F. Ellis, Mary E. Weybright | 2003-12-30 |
| 6664161 | Method and structure for salicide trench capacitor plate electrode | Michael P. Chudzik, Carl Radens, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic Shafer +1 more | 2003-12-16 |
| 6656807 | Grooved planar DRAM transfer device using buried pocket | Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak | 2003-12-02 |
| 6653678 | Reduction of polysilicon stress in trench capacitors | Dureseti Chidambarrao, Rajarao Jammy | 2003-11-25 |
| 6649935 | Self-aligned, planarized thin-film transistors, devices employing the same | Louis L. Hsu, William R. Tonti, Li-Kong Wang | 2003-11-18 |
| 6646949 | Word line driver for dynamic random access memories | Wayne F. Ellis, Louis L. Hsu, William R. Tonti | 2003-11-11 |
| 6642566 | Asymmetric inside spacer for vertical transistor | Ramachandra Divakaruni, Haining Yang | 2003-11-04 |
| 6635525 | Method of making backside buried strap for SOI DRAM trench capacitor | Herbert L. Ho | 2003-10-21 |
| 6632741 | Self-trimming method on looped patterns | Lawrence A. Clevenger, Louis L. Hsu, Carl Radens | 2003-10-14 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch | Ramachandra Divakaruni, Carl Radens, Ulrike Gruening | 2003-10-07 |
| 6617702 | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate | Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Tsorng-Dih Yuan | 2003-09-09 |
| 6614074 | Grooved planar DRAM transfer device using buried pocket | Gary B. Bronner, Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak | 2003-09-02 |
| 6605838 | Process flow for thick isolation collar with reduced length | Rama Divakaruni, Gerd Fehlauer, Stephan Kudelka, Uwe Schroeder, Helmut Tews | 2003-08-12 |
| 6596592 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, William R. Tonti | 2003-07-22 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | James W. Adkisson, Ramachandra Divakaruni, Jeffrey P. Gambino | 2003-07-08 |
| 6580136 | Method for delineation of eDRAM support device notched gate | Carl Radens | 2003-06-17 |
| 6576945 | Structure and method for a compact trench-capacitor DRAM cell with body contact | Carl Radens | 2003-06-10 |
| 6573561 | Vertical MOSFET with asymmetrically graded channel doping | Dureseti Chidambarrao, Ramachandra Divakaruni, Kevin McStay | 2003-06-03 |
| 6573585 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Dureseti Chidambarrao, Louis L. Hsu, Carl Radens | 2003-06-03 |
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening, Stephan Kudelka +5 more | 2003-06-03 |
| 6570207 | Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex | Louis L. Hsu, Carl Radens, William R. Tonti | 2003-05-27 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI | Ramachandra Divakaruni, Carl Radens, Gary B. Bronner | 2003-05-27 |
| 6566228 | Trench isolation processes using polysilicon-assisted fill | Jochen Beintner, Rama Divakaruni, Andreas Knorr | 2003-05-20 |
| 6566191 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Carl Radens, Richard Strub, William R. Tonti | 2003-05-20 |
| 6566177 | Silicon-on-insulator vertical array device trench capacitor DRAM | Carl Radens, Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Dan Moy +3 more | 2003-05-20 |