Issued Patents 2003
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6563736 | Flash memory structure having double celled elements and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Carl Radens, William R. Tonti | 2003-05-13 |
| 6555862 | Self-aligned buried strap for vertical transistors | Ulrike Gruening, Alexander Michaelis | 2003-04-29 |
| 6552378 | Ultra compact DRAM cell and method of making | Heinz Hoenigschmid, Louis L. Hsu | 2003-04-22 |
| 6548358 | Electrically blowable fuse with reduced cross-sectional area | Kenneth C. Arndt, Dureseti Chidambarrao, Louis L. Hsu, Carl Radens | 2003-04-15 |
| 6544837 | SOI stacked DRAM logic | Ramachandra Divakauni, Mark C. Hakey, William H. Ma, William R. Tonti | 2003-04-08 |
| 6541815 | High-density dual-cell flash memory structure | Louis L. Hsu, Chung H. Lam, Carl Radens | 2003-04-01 |
| 6538295 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Carl Radens, William R. Tonti | 2003-03-25 |
| 6534824 | Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell | Dureseti Chidambarrao | 2003-03-18 |
| 6531410 | Intrinsic dual gate oxide MOSFET using a damascene gate process | Claude L. Bertin, Anthony J. Dally, John A. Fifield, John Jesse Higgins, William R. Tonti +1 more | 2003-03-11 |
| 6528855 | MOSFET having a low aspect ratio between the gate and the source/drain | Qiuyi Ye, William R. Tonti, Yujun Li | 2003-03-04 |
| 6524941 | Sub-minimum wiring structure | Louis L. Hsu | 2003-02-25 |
| 6518119 | Strap with intrinsically conductive barrier | Jeffrey P. Gambino, Rajarao Jammy, Carl Radens | 2003-02-11 |
| 6518118 | Structure and process for buried bitline and single sided buried conductor formation | Satish D. Athavale, Ramachandra Divakaruni | 2003-02-11 |
| 6518112 | High performance, low power vertical integrated CMOS devices | Michael D. Armacost, Claude L. Bertin, Erik L. Hedberg | 2003-02-11 |
| 6518670 | Electrically porous on-chip decoupling/shielding layer | Ronald G. Filippi, Jeffrey P. Gambino, Richard A. Wachnik | 2003-02-11 |
| 6518641 | Deep slit isolation with controlled void | Ramachandra Divakaruni, Johnathan E. Faltermeier, William R. Tonti | 2003-02-11 |
| 6512275 | Semiconductor integrated circuits | Louis L. Hsu | 2003-01-28 |
| 6509226 | Process for protecting array top oxide | Venkatachalam C. Jaiprakash, Ramachandra Divakaruni, Rajeev Malik, Mihel Seitz | 2003-01-21 |
| 6504210 | Fully encapsulated damascene gates for Gigabit DRAMs | Ramachandra Divakaruni, Jeffrey P. Gambino, Viraj Y. Sardesai, Mary E. Weybright | 2003-01-07 |