Issued Patents 2003
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670234 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof | Louis L. Hsu, Li-Kong Wang | 2003-12-30 |
| 6664161 | Method and structure for salicide trench capacitor plate electrode | Michael P. Chudzik, Jack A. Mandelman, Rajarao Jammy, Kenneth T. Settlemyer, Jr., Padraic Shafer +1 more | 2003-12-16 |
| 6632741 | Self-trimming method on looped patterns | Lawrence A. Clevenger, Louis L. Hsu, Jack A. Mandelman | 2003-10-14 |
| 6630379 | Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch | Jack A. Mandelman, Ramachandra Divakaruni, Ulrike Gruening | 2003-10-07 |
| 6617702 | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate | Louis L. Hsu, Rajiv V. Joshi, Jack A. Mandelman, Tsorng-Dih Yuan | 2003-09-09 |
| 6580136 | Method for delineation of eDRAM support device notched gate | Jack A. Mandelman | 2003-06-17 |
| 6576945 | Structure and method for a compact trench-capacitor DRAM cell with body contact | Jack A. Mandelman | 2003-06-10 |
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening +5 more | 2003-06-03 |
| 6570208 | 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Ramachandra Divakaruni, Gary B. Bronner | 2003-05-27 |
| 6570207 | Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex | Louis L. Hsu, Jack A. Mandelman, William R. Tonti | 2003-05-27 |
| 6566238 | Metal wire fuse structure with cavity | Axel Brintzinger, Edward W. Kiewra, Chandrasekhar Narayan | 2003-05-20 |
| 6566177 | Silicon-on-insulator vertical array device trench capacitor DRAM | Gary B. Bronner, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy +3 more | 2003-05-20 |
| 6566191 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Richard Strub, William R. Tonti | 2003-05-20 |
| 6563160 | High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2003-05-13 |
| 6563736 | Flash memory structure having double celled elements and method for fabricating the same | Louis L. Hsu, Rajiv V. Joshi, Jack A. Mandelman, William R. Tonti | 2003-05-13 |
| 6556477 | Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same | Louis L. Hsu, Li-Kong Wang | 2003-04-29 |
| 6541815 | High-density dual-cell flash memory structure | Jack A. Mandelman, Louis L. Hsu, Chung H. Lam | 2003-04-01 |
| 6538295 | Salicide device with borderless contact | Gary B. Bronner, Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, William R. Tonti | 2003-03-25 |
| 6518119 | Strap with intrinsically conductive barrier | Jeffrey P. Gambino, Rajarao Jammy, Jack A. Mandelman | 2003-02-11 |
| 6518616 | Vertical gate top engineering for improved GC and CB process windows | Thomas W. Dyer, Stephan Kudelka, Venkatachaiam C. Jaiprakash | 2003-02-11 |
| 6509624 | Semiconductor fuses and antifuses in vertical DRAMS | Wolfgang Bergner, Rama Divakaruni, Larry Nesbit | 2003-01-21 |
| 6509612 | High dielectric constant materials as gate dielectrics (insulators) | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2003-01-21 |