Issued Patents 2003
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670235 | Process flow for two-step collar in DRAM preparation | Helmut Tews, Oliver Genz | 2003-12-30 |
| 6613642 | Method for surface roughness enhancement in semiconductor capacitor manufacturing | Stephen Rahn, Irene McStay, Helmut Tews, Uwe Schroeder, Rajarao Jammy | 2003-09-02 |
| 6605860 | Semiconductor structures and manufacturing methods | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Raj Jammy, Ulrike Gruening | 2003-08-12 |
| 6605838 | Process flow for thick isolation collar with reduced length | Jack A. Mandelman, Rama Divakaruni, Gerd Fehlauer, Uwe Schroeder, Helmut Tews | 2003-08-12 |
| 6599798 | Method of preparing buried LOCOS collar in trench DRAMS | Helmut Tews, Uwe Schroeder, Rolf Weis | 2003-07-29 |
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening +5 more | 2003-06-03 |
| 6566273 | Etch selectivity inversion for etching along crystallographic directions in silicon | — | 2003-05-20 |
| 6559002 | Rough oxide hard mask for DT surface area enhancement for DT DRAM | Helmut Tews, Stephen Rahn, Irene McStay, Uwe Schroeder | 2003-05-06 |
| 6555430 | Process flow for capacitance enhancement in a DRAM trench | Michael P. Chudzik, Johnathan E. Faltermeier, Rajarao Jammy, Irene McStay, Kenneth T. Settlemyer, Jr. +1 more | 2003-04-29 |
| 6548344 | Spacer formation process using oxide shield | Jochen Beintner, Thomas W. Dyer | 2003-04-15 |
| 6518616 | Vertical gate top engineering for improved GC and CB process windows | Thomas W. Dyer, Venkatachaiam C. Jaiprakash, Carl Radens | 2003-02-11 |