RS

Ramkumar Subramanian

AM AMD: 47 patents #3 of 1,128Top 1%
📍 San Diego, CA: #1 of 1,657 inventorsTop 1%
🗺 California: #4 of 26,763 inventorsTop 1%
Overall (2002): #21 of 266,432Top 1%
47
Patents 2002

Issued Patents 2002

Showing 26–47 of 47 patents

Patent #TitleCo-InventorsDate
6429116 Method of fabricating a slot dual damascene structure without middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-08-06
6426301 Reduction of via etch charging damage through the use of a conducting hard mask Jeffrey A. Shields, Bharath Rangarajan, Allen S. Yu 2002-07-30
6423479 Cleaning carbon contamination on mask using gaseous phase Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo 2002-07-23
6417084 T-gate formation using a modified conventional poly process Bhanwar Singh, Marina V. Plat, Christopher F. Lyons 2002-07-09
6413857 Method of creating ground to avoid charging in SOI products Bharath Rangarajan, Bhanwar Singh 2002-07-02
6403456 T or T/Y gate formation using trim etch processing Marina V. Plat, Christopher F. Lyons, Bhanwar Singh 2002-06-11
6391766 Method of making a slot via filled dual damascene structure with middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-05-21
6383952 RELACS process to double the frequency or pitch of small feature formation Bhanwar Singh, Marina V. Plat, Christopher F. Lyons, Scott A. Bell 2002-05-07
6383919 Method of making a dual damascene structure without middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-05-07
6380067 Method for creating partially UV transparent anti-reflective coating for semiconductors Minh Van Ngo, Suzette K. Pangrle, Kashmir Sahota, Christopher F. Lyons 2002-04-30
6376389 Method for eliminating anti-reflective coating in semiconductors Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita, Fei Wang +1 more 2002-04-23
6372614 Dual damascene method for backened metallization using poly stop layers Bharath Rangarajan, Bhanwar Singh 2002-04-16
6372635 Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-04-16
6372631 Method of making a via filled dual damascene structure without middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-04-16
6371134 Ozone cleaning of wafers Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo 2002-04-16
6365505 Method of making a slot via filled dual damascene structure with middle stop layer Fei Wang, Lynne A. Okada, Calvin T. Gabriel 2002-04-02
6365509 Semiconductor manufacturing method using a dielectric photomask Wenge Yang, Marina V. Plat, Lewis Shen 2002-04-02
6358856 Bright field image reversal for contact hole patterning Christopher F. Lyons, Marina V. Plat, Todd P. Lukanc 2002-03-19
6354133 Use of carbon nanotubes to calibrate conventional tips used in AFM Sanjay K. Yedur, Bhanwar Singh, Bryan K. Choo, Michael K. Templeton 2002-03-12
6348379 Method of forming self-aligned contacts using consumable spacers Fei Wang, Yu Sun 2002-02-19
6348406 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating Minh Van Ngo, Kashmir Sahota, YongZhong Hu, Hiroyuki Kinoshita, Fei Wang +1 more 2002-02-19
6335152 Use of RTA furnace for photoresist baking Bharath Rangarajan, Michael K. Templeton, Bhanwar Singh 2002-01-01