Issued Patents 2002
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6495447 | Use of hydrogen doping for protection of low-k dielectric layers | Lynne A. Okada | 2002-12-17 |
| 6475929 | Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant | Suzette K. Pangrle, Lynne A. Okada, Fei Wang | 2002-11-05 |
| 6472231 | Dielectric layer with treated top surface forming an etch stop layer and method of making the same | Lynne A. Okada | 2002-10-29 |
| 6465889 | Silicon carbide barc in dual damascene processing | Ramkumar Subramanian, Fei Wang, Lynne A. Okada, Darrell M. Erb | 2002-10-15 |
| 6465340 | Via filled dual damascene structure with middle stop layer and method for making the same | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-10-15 |
| 6451673 | Carrier gas modification for preservation of mask layer during plasma etching | Lynne A. Okada | 2002-09-17 |
| 6448654 | Ultra thin etch stop layer for damascene process | Lynne A. Okada | 2002-09-10 |
| 6444573 | Method of making a slot via filled dual damascene structure with a middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-09-03 |
| 6429116 | Method of fabricating a slot dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-08-06 |
| 6410210 | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides | — | 2002-06-25 |
| 6391766 | Method of making a slot via filled dual damascene structure with middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-05-21 |
| 6387720 | Waveguide structures integrated with standard CMOS circuitry and methods for making the same | Michael N. Misheloff, Subhas Bothra, Milind Weling | 2002-05-14 |
| 6383919 | Method of making a dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-05-07 |
| 6380092 | Gas phase planarization process for semiconductor wafers | Rao Annapragada, Milind Weling | 2002-04-30 |
| 6372635 | Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-16 |
| 6372631 | Method of making a via filled dual damascene structure without middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-16 |
| 6365505 | Method of making a slot via filled dual damascene structure with middle stop layer | Fei Wang, Lynne A. Okada, Ramkumar Subramanian | 2002-04-02 |
| 6361706 | Method for reducing the amount of perfluorocompound gas contained in exhaust emissions from plasma processing | — | 2002-03-26 |
| 6342428 | Method for a consistent shallow trench etch profile | Tammy Zheng, Edward Yeh | 2002-01-29 |