Issued Patents 2002
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6501534 | Automated periodic focus and exposure calibration of a lithography stepper | Bhanwar Singh, Bharath Rangarajan, Carmen Morales | 2002-12-31 |
| 6492075 | Chemical trim process | Michael K. Templeton, Bharath Rangarajan | 2002-12-10 |
| 6486078 | Super critical drying of low k materials | Bharath Rangarajan, Bhanwar Singh | 2002-11-26 |
| 6482699 | Method for forming self-aligned contacts and local interconnects using decoupled local interconnect process | YongZhong Hu, Fei Wang, Wenge Yang, Yu Sun | 2002-11-19 |
| 6482558 | Conducting electron beam resist thin film layer for patterning of mask plates | Bhanwar Singh, Bharath Rangarajan | 2002-11-19 |
| 6479820 | Electrostatic charge reduction of photoresist pattern on development track | Bhanwar Singh, Bharath Rangarajan, Khoi A. Phan, Bryan K. Choo | 2002-11-12 |
| 6475905 | Optimization of organic bottom anti-reflective coating (BARC) thickness for dual damascene process | Christopher Lee Pike | 2002-11-05 |
| 6475904 | Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques | Uzodinma Okoroanyanwu | 2002-11-05 |
| 6465889 | Silicon carbide barc in dual damascene processing | Fei Wang, Lynne A. Okada, Calvin T. Gabriel, Darrell M. Erb | 2002-10-15 |
| 6465340 | Via filled dual damascene structure with middle stop layer and method for making the same | Fei Wang, Lynne A. Okada, Calvin T. Gabriel | 2002-10-15 |
| 6458691 | Dual inlaid process using an imaging layer to protect via from poisoning | Christopher F. Lyons, Marina V. Plat, Bhanwar Singh | 2002-10-01 |
| 6459482 | Grainless material for calibration sample | Bhanwar Singh, Khoi A. Phan, Bharath Rangarajan, Michael K. Templeton, Sanjay K. Yedur +1 more | 2002-10-01 |
| 6459155 | Damascene processing employing low Si-SiON etch stop layer/arc | Dawn Hopper, Minh Van Ngo | 2002-10-01 |
| 6458607 | Using UV/VIS spectrophotometry to regulate developer solution during a development process | Bharath Rangarajan, Bhanwar Singh | 2002-10-01 |
| 6455416 | Developer soluble dyed BARC for dual damascene process | Bhanwar Singh, Bharath Rangarajan, Michael K. Templeton | 2002-09-24 |
| 6455409 | Damascene processing using a silicon carbide hard mask | Dawn Hopper | 2002-09-24 |
| 6451621 | Using scatterometry to measure resist thickness and control implant | Bharath Rangarajan, Bhanwar Singh | 2002-09-17 |
| 6451512 | UV-enhanced silylation process to increase etch resistance of ultra thin resists | Bharath Rangarajan, Khoi A. Phan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur +1 more | 2002-09-17 |
| 6448164 | Dark field image reversal for gate or line patterning | Christopher F. Lyons, Marina V. Plat, Todd P. Lukanc | 2002-09-10 |
| 6448097 | Measure fluorescence from chemical released during trim etch | Bhanwar Singh, Bharath Rangarajan | 2002-09-10 |
| 6444373 | Modification of mask layout data to improve mask fidelity | Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan | 2002-09-03 |
| 6444381 | Electron beam flood exposure technique to reduce the carbon contamination | Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Khoi A. Phan, Bryan K. Choo +1 more | 2002-09-03 |
| 6444573 | Method of making a slot via filled dual damascene structure with a middle stop layer | Fei Wang, Lynne A. Okada, Calvin T. Gabriel | 2002-09-03 |
| 6445072 | Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant | Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan | 2002-09-03 |
| 6429121 | Method of fabricating dual damascene with silicon carbide via mask/ARC | Dawn Hopper, Richard J. Huang | 2002-08-06 |