Issued Patents 2002
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6479350 | Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers | Zicheng Gary Ling, Raymond T. Lee | 2002-11-12 |
| 6472317 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Fei Wang, Jerry Cheng, Simon S. Chan | 2002-10-29 |
| 6458606 | Etch bias distribution across semiconductor wafer | Marina V. Plat, Luigi Capodieci, Scott A. Bell | 2002-10-01 |
| 6448164 | Dark field image reversal for gate or line patterning | Christopher F. Lyons, Ramkumar Subramanian, Marina V. Plat | 2002-09-10 |
| 6383827 | Electrical alignment test structure using local interconnect ladder resistor | Asim A. Selcuk | 2002-05-07 |
| 6358856 | Bright field image reversal for contact hole patterning | Christopher F. Lyons, Ramkumar Subramanian, Marina V. Plat | 2002-03-19 |
| 6355511 | Method of providing a frontside contact to substrate of SOI device | Kurt Taylor | 2002-03-12 |
| 6350687 | Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film | Steven C. Avanzino, Kai Yang, Sergey Lopatin | 2002-02-26 |