Issued Patents 2002
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500743 | Method of copper-polysilicon T-gate formation | Sergey Lopatin, Matthew S. Buynoski | 2002-12-31 |
| 6500754 | Anneal hillock suppression method in integrated circuit interconnects | Darrell M. Erb, Alline F. Myers | 2002-12-31 |
| 6469385 | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | Pin-Chin Connie Wang, Minh Van Ngo | 2002-10-22 |
| 6465156 | Method for mitigating formation of silicon grass | Bhanwar Singh, Bharath Rangarajan | 2002-10-15 |
| 6454916 | Selective electroplating with direct contact chemical polishing | Fei Wang, Darrell M. Erb | 2002-09-24 |
| 6432822 | Method of improving electromigration resistance of capped Cu | Minh Van Ngo, Amit P. Marathe | 2002-08-13 |
| 6433379 | Tantalum anodization for in-laid copper metallization capacitor | Sergey Lopatin, Qi Xiang, Matthew S. Buynoski | 2002-08-13 |
| 6422918 | Chemical-mechanical polishing of photoresist layer | Bhanwar Singh, Bharath Rangarajan, Alvin M. Dangca | 2002-07-23 |
| 6417100 | Annealing ambient in integrated circuit interconnects | Pin-Chin Connie Wang, Minh Van Ngo | 2002-07-09 |
| 6413869 | Dielectric protected chemical-mechanical polishing in integrated circuit interconnects | Krishnashree Achuthan, Kashmir Sahota | 2002-07-02 |
| 6410443 | Method for removing semiconductor ARC using ARC CMP buffing | Stephen Keetai Park, Kashmir Sahota, David Matsumoto, Mark T. Ramsbey | 2002-06-25 |
| 6403474 | Controlled anneal conductors for integrated circuit interconnects | Pin-Chin Connie Wang, Minh Van Ngo | 2002-06-11 |
| 6352817 | Methodology for mitigating formation of t-tops in photoresist | Bharath Rangarajan, Bhanwar Singh | 2002-03-05 |
| 6350687 | Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film | Kai Yang, Sergey Lopatin, Todd P. Lukanc | 2002-02-26 |
| 6346466 | Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation | Steven K. Park | 2002-02-12 |