Issued Patents All Time
Showing 76–100 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9390219 | System for and method of semiconductor fault detection | Yuan-Han Lee | 2016-07-12 |
| 9391110 | Wafer on wafer stack method of forming and method of using the same | Yun-Han Lee | 2016-07-12 |
| 9341672 | Method and apparatus for interconnect test | Saman M. I. Adham | 2016-05-17 |
| 9222983 | Circuit and method for monolithic stacked integrated circuit testing | — | 2015-12-29 |
| 9194913 | Circuit and method for diagnosing scan chain failures | — | 2015-11-24 |
| 9158881 | Interposer defect coverage metric and method to maximize the same | Ashok Mehta | 2015-10-13 |
| 9110136 | Circuit and method for monolithic stacked integrated circuit testing | Ashok Mehta | 2015-08-18 |
| 9054101 | Multi-dimensional integrated circuit structures and methods of forming the same | Mark Semmelmeyer | 2015-06-09 |
| 9047432 | System and method for validating stacked dies by comparing connections | Ashok Mehta, Stanley John, Kai-Yuan Ting, Chao-Yang Yeh | 2015-06-02 |
| 9041411 | Testing of an integrated circuit that contains secret information | Erik Jan Marinissen, Andre Krijn Nieuwland, Hubertus G. H. Vermuelen, Hendrikus Petrus Elisabeth Vranken | 2015-05-26 |
| 8972918 | System and method for functional verification of multi-die 3D ICs | Stanley John, Ashok Mehta, Kai-Yuan Ting | 2015-03-03 |
| 8966419 | System and method for testing stacked dies | Ashok Mehta | 2015-02-24 |
| 8914692 | DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips | — | 2014-12-16 |
| 8873320 | DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips | Tze-Chiang Huang | 2014-10-28 |
| 8836363 | Probe card partition scheme | Mill-Jer Wang | 2014-09-16 |
| 8826202 | Reducing design verification time while maximizing system functional coverage | Ashok Mehta | 2014-09-02 |
| 8751994 | System and method for testing stacked dies | — | 2014-06-10 |
| 8707238 | Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs | Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Yun-Han Lee +1 more | 2014-04-22 |
| 8686570 | Multi-dimensional integrated circuit structures and methods of forming the same | Mark Semmelmeyer | 2014-04-01 |
| 8627160 | System and device for reducing instantaneous voltage droop during a scan shift operation | Narendra Devta-Prasanna, Arun Gunda | 2014-01-07 |
| 8578309 | Format conversion from value change dump (VCD) to universal verification methodology (UVM) | Ashok Mehta, Stanley John, Kai-Yuan Ting | 2013-11-05 |
| 8566657 | Circuit and method for diagnosing scan chain failures | — | 2013-10-22 |
| 8566766 | Method for detecting small delay defects | Saurabh Gupta, Wei-Pin Changchien, Chin-Chou Liu | 2013-10-22 |
| 8561001 | System and method for testing stacked dies | — | 2013-10-15 |
| 8552734 | Test prepared integrated circuit with an internal power supply domain | Rinze Ida Mechtildis Peter Meijer, Jose De Jesus Pineda De Gyvez | 2013-10-08 |