Issued Patents All Time
Showing 101–107 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8515695 | Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC | Narendra Devta-Prasanna | 2013-08-20 |
| 8436639 | Circuits and methods for testing through-silicon vias | — | 2013-05-07 |
| 8402404 | Stacked die interconnect validation | Ashok Mehta, Stanley John, Kai-Yuan Ting, Chao-Yang Yeh | 2013-03-19 |
| 8352818 | Method for generating test patterns for small delay defects | Narendra Devta-Prasanna, Ritesh P. Turakhia | 2013-01-08 |
| 8140923 | Test circuit and method for testing of infant mortality related defects | Narendra Devta-Prasanna | 2012-03-20 |
| 7380181 | Test circuit and method for hierarchical core | — | 2008-05-27 |
| 7076709 | Testing of circuit with plural clock domains | Hubertus Gerardus Hendrikus Vermeulen | 2006-07-11 |