ND

Narendra Devta-Prasanna

LS Lsi: 9 patents #135 of 1,740Top 8%
Lsi Logic: 1 patents #1,146 of 1,957Top 60%
Overall (All Time): #515,010 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8627160 System and device for reducing instantaneous voltage droop during a scan shift operation Sandeep Kumar Goel, Arun Gunda 2014-01-07
8515695 Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC Sandeep Kumar Goel 2013-08-20
8412994 Design-for-test technique to reduce test volume including a clock gate controller 2013-04-02
8352818 Method for generating test patterns for small delay defects Sandeep Kumar Goel, Ritesh P. Turakhia 2013-01-08
8140923 Test circuit and method for testing of infant mortality related defects Sandeep Kumar Goel 2012-03-20
7802159 Enhanced logic built-in self-test module and method of online system testing employing the same Sreejit Chakravarty, Fan Yang 2010-09-21
7555688 Method for implementing test generation for systematic scan reconfiguration in an integrated circuit Ahmad Alvamani, Arun Gunda 2009-06-30
7461307 System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop Arun Gunda 2008-12-02
7461315 Method and system for improving quality of a circuit through non-functional test pattern identification Arun Gunda 2008-12-02
7293210 System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop Arun Gunda 2007-11-06