RT

Ritesh P. Turakhia

LS Lsi: 1 patents #914 of 1,740Top 55%
Lsi Logic: 1 patents #1,146 of 1,957Top 60%
📍 Portland, OR: #4,612 of 9,213 inventorsTop 55%
🗺 Oregon: #12,654 of 28,073 inventorsTop 50%
Overall (All Time): #2,064,418 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
8352818 Method for generating test patterns for small delay defects Sandeep Kumar Goel, Narendra Devta-Prasanna 2013-01-08
7171638 Methods of screening ASIC defects using independent component analysis of quiescent current measurements Robert Brady Benware 2007-01-30