Robert Brady Benware — 20 Patents at Mentor Graphics

Robert Brady Benware has been granted 20 US patents while listed as an inventor at Mentor Graphics. The first was granted in 2005 and the most recent in December 2019. Robert Brady Benware ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Robert Brady Benware in Sandy, OR, US.

Patents per Year

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Showing 1–20 of 20 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10496779	Generating root cause candidates for yield analysis	Wu-Tung Cheng, Christopher W. Schuermyer, Jonathan James Muirhead, Chen-Yi Chang	2019-12-03
10234502	Circuit defect diagnosis based on sink cell fault models	Huaxing Tang, Manish Sharma, Wu-Tung Cheng	2019-03-19
10198548	Identifying the defective layer of a yield excursion through the statistical analysis of scan diagnosis results	Manish Sharma	2019-02-05
9857421	Dynamic design partitioning for diagnosis	Huaxing Tang, Yu Huang, Wu-Tung Cheng, Xiaoxin Fan	2018-01-02
9443051	Generating root cause candidates for yield analysis	Wu-Tung Cheng, Christopher W. Schuermyer, Jonathan James Muirhead, Chen-Yi Chang	2016-09-13	$12,797,000
9378327	Canonical forms of layout patterns	Wu-Tung Cheng, Manish Sharma, Robert R. Klingenberg	2016-06-28	$10,664,000
9336107	Dynamic design partitioning for diagnosis	Huaxing Tang, Yu Huang, Wu-Tung Cheng, Xiaoxin Fan	2016-05-10	$5,221,000
9244125	Dynamic design partitioning for scan chain diagnosis	Yu Huang, Huaxing Tang, Wu-Tung Cheng, Manish Sharma, Xiaoxin Fan	2016-01-26	$18,769,000
9026874	Test access mechanism for diagnosis based on partitioning scan chains	Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Mark Kassab	2015-05-05	$6,453,000
8930782	Root cause distribution determination based on layout aware scan diagnosis results	—	2015-01-06	$2,525,000
8707232	Fault diagnosis based on design partitioning	Huaxing Tang, Wu-Tung Cheng, Xiaoxin Fan	2014-04-22	$9,712,000
8607107	Test access mechanism for diagnosis based on partitioining scan chains	Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Mark Kassab	2013-12-10	$5,152,000
7617427	Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures	Steven L. Haehn	2009-11-10	$11,137,000
7395478	Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics	—	2008-07-01	$7,094,000
7216280	Method of generating test patterns to efficiently screen inline resistance delay defects in complex ASICs	—	2007-05-08	$9,099,000
7171638	Methods of screening ASIC defects using independent component analysis of quiescent current measurements	Ritesh P. Turakhia	2007-01-30	$4,044,000
7079963	Modified binary search for optimizing efficiency of data collection time	Cary Gloor, Robert Madge	2006-07-18	$3,159,000
7058909	Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design	Cam Luong Lu, Thai M. Nguyen	2006-06-06	$5,097,000
6972592	Self-timed scan circuit for ASIC fault testing	—	2005-12-06	$2,844,000
6954705	Method of screening defects using low voltage IDDQ measurement	—	2005-10-11	$6,537,000

Robert Brady Benware — 20 Patents

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