RB

Robert Brady Benware

MG Mentor Graphics: 12 patents #18 of 698Top 3%
Lsi Logic: 6 patents #302 of 1,957Top 20%
LS Lsi: 2 patents #602 of 1,740Top 35%
Overall (All Time): #222,326 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10496779 Generating root cause candidates for yield analysis Wu-Tung Cheng, Christopher W. Schuermyer, Jonathan James Muirhead, Chen-Yi Chang 2019-12-03
10234502 Circuit defect diagnosis based on sink cell fault models Huaxing Tang, Manish Sharma, Wu-Tung Cheng 2019-03-19
10198548 Identifying the defective layer of a yield excursion through the statistical analysis of scan diagnosis results Manish Sharma 2019-02-05
9857421 Dynamic design partitioning for diagnosis Huaxing Tang, Yu Huang, Wu-Tung Cheng, Xiaoxin Fan 2018-01-02
9443051 Generating root cause candidates for yield analysis Wu-Tung Cheng, Christopher W. Schuermyer, Jonathan James Muirhead, Chen-Yi Chang 2016-09-13
9378327 Canonical forms of layout patterns Wu-Tung Cheng, Manish Sharma, Robert R. Klingenberg 2016-06-28
9336107 Dynamic design partitioning for diagnosis Huaxing Tang, Yu Huang, Wu-Tung Cheng, Xiaoxin Fan 2016-05-10
9244125 Dynamic design partitioning for scan chain diagnosis Yu Huang, Huaxing Tang, Wu-Tung Cheng, Manish Sharma, Xiaoxin Fan 2016-01-26
9026874 Test access mechanism for diagnosis based on partitioning scan chains Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Mark Kassab 2015-05-05
8930782 Root cause distribution determination based on layout aware scan diagnosis results 2015-01-06
8707232 Fault diagnosis based on design partitioning Huaxing Tang, Wu-Tung Cheng, Xiaoxin Fan 2014-04-22
8607107 Test access mechanism for diagnosis based on partitioining scan chains Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Mark Kassab 2013-12-10
7617427 Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures Steven L. Haehn 2009-11-10
7395478 Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics 2008-07-01
7216280 Method of generating test patterns to efficiently screen inline resistance delay defects in complex ASICs 2007-05-08
7171638 Methods of screening ASIC defects using independent component analysis of quiescent current measurements Ritesh P. Turakhia 2007-01-30
7079963 Modified binary search for optimizing efficiency of data collection time Cary Gloor, Robert Madge 2006-07-18
7058909 Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design Cam Luong Lu, Thai M. Nguyen 2006-06-06
6972592 Self-timed scan circuit for ASIC fault testing 2005-12-06
6954705 Method of screening defects using low voltage IDDQ measurement 2005-10-11