Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7490307 | Automatic generating of timing constraints for the validation/signoff of test structures | Giuseppe Fomaciari, Fabio Mazza, William Wu Shen | 2009-02-10 |
| 7444560 | Test clocking scheme | Thai M. Nguyen, William Wu Shen | 2008-10-28 |
| 7058909 | Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design | Robert Brady Benware, Thai M. Nguyen | 2006-06-06 |