AR

Angelique Raley

TL Tokyo Electron Limited: 56 patents #41 of 5,567Top 1%
📍 Albany, NY: #23 of 790 inventorsTop 3%
🗺 New York: #1,555 of 115,490 inventorsTop 2%
Overall (All Time): #43,916 of 4,157,543Top 2%
56
Patents All Time

Issued Patents All Time

Showing 26–50 of 56 patents

Patent #TitleCo-InventorsDate
11361993 Method for inverse via patterning for back end of line dual damascene structures Katie Lutker-Lee 2022-06-14
11333968 Method for reducing lithography defects and pattern transfer Eric Chih-Fang Liu, Nihar Mohanty 2022-05-17
11322364 Method of patterning a metal film with improved sidewall roughness Nicholas Joy 2022-05-03
11289325 Radiation of substrates during processing and systems thereof Michael Edley, Xinghua Sun, Yen-Tien Lu, Henan Zhang, Hiroyuki Suzuki +1 more 2022-03-29
11227767 Critical dimension trimming method designed to minimize line width roughness and line edge roughness Kal Subhadeep 2022-01-18
11164781 ALD (atomic layer deposition) liner for via profile control and related applications Xinghua Sun, Yen-Tien Lu, David L. O'Meara, Jeffrey Smith 2021-11-02
11127594 Manufacturing methods for mandrel pull from spacers for multi-color patterning Xinghua Sun, Andrew Metz 2021-09-21
11101173 Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same Robert D. Clark, Jeffrey Smith, Kandabara Tapily, Qiang Zhao 2021-08-24
10971372 Gas phase etch with controllable etch selectivity of Si-containing arc or silicon oxynitride to different films or masks Subhadeep Kal, Nihar Mohanty, Aelan Mosden, Scott Lefevre 2021-04-06
10964587 Atomic layer deposition for low-K trench protection during etch Yen-Tien Lu, David L. O'Meara, Xinghua Sun 2021-03-30
10950460 Method utilizing using post etch pattern encapsulation Andrew Metz, Cory Wajda, Junling Sun 2021-03-16
10916472 Self-aware and correcting heterogenous platform incorporating integrated semiconductor processing modules and method for using same Robert D. Clark, Jeffrey Smith, Kandabara Tapily, Qiang Zhao 2021-02-09
10867854 Double plug method for tone inversion patterning 2020-12-15
10854453 Method for reducing reactive ion etch lag in low K dielectric etching Christopher Cole, Andrew Metz 2020-12-01
10748769 Methods and systems for patterning of low aspect ratio stacks Elliott Franke, Sophie Thibaut 2020-08-18
10727057 Platform and method of operating for integrated end-to-end self-aligned multi-patterning process Robert D. Clark, Richard A. Farrell, Kandabara Tapily, Sophie Thibaut 2020-07-28
10580660 Gas phase etching system and method Subhadeep Kal, Nihar Mohanty, Aelan Mosden, Scott Lefevre 2020-03-03
10497575 Method for increasing trench CD in EUV patterning without increasing single line opens or roughness Jeffrey Shearer 2019-12-03
10453686 In-situ spacer reshaping for self-aligned multi-patterning methods and systems Eric Chih-Fang Liu, Akiteru Ko 2019-10-22
10354873 Organic mandrel protection process Akiteru Ko, Sophie Thibaut, Satoru Nakamura, Nihar Mohanty 2019-07-16
10049875 Trim method for patterning during various stages of an integration scheme Akiteru Ko 2018-08-14
9786503 Method for increasing pattern density in self-aligned patterning schemes without using hard masks Nihar Mohanty, Akiteru Ko 2017-10-10
9748110 Method and system for selective spacer etch for multi-patterning schemes Subhadeep Kal, Nihar Mohanty, Aelan Mosden 2017-08-29
9673059 Method for increasing pattern density in self-aligned patterning integration schemes Akiteru Ko 2017-06-06
9443731 Material processing to achieve sub-10nm patterning David L. O'Meara, Akiteru Ko, Kiyohito Ito 2016-09-13