Issued Patents All Time
Showing 51–56 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9257280 | Mitigation of asymmetrical profile in self aligned patterning etch | Akiteru Ko, Kiyohito Ito | 2016-02-09 |
| 9171736 | Spacer material modification to improve K-value and etch properties | David L. O'Meara | 2015-10-27 |
| 9165765 | Method for patterning differing critical dimensions at sub-resolution scales | Akiteru Ko | 2015-10-20 |
| 9111746 | Method for reducing damage to low-k gate spacer during etching | Alok Ranjan | 2015-08-18 |
| 8906760 | Aspect ratio dependent deposition to improve gate spacer profile, fin-loss and hardmask-loss for FinFET scheme | Alok Ranjan | 2014-12-09 |
| 8664125 | Highly selective spacer etch process with reduced sidewall spacer slimming | Takuya Mori, Hiroto Ohtake | 2014-03-04 |