Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7183165 | Reliable high voltage gate dielectric layers using a dual nitridation process | Rajesh Khamankar, Hiroaki Niimi, April Gurba, Toan Tran, James Joseph Chambers | 2007-02-27 |
| 6933248 | Method for transistor gate dielectric layer with uniform nitrogen concentration | — | 2005-08-23 |
| 6737333 | Semiconductor device isolation structure and method of forming | Zhihao Chen, Freidoon Mehrad | 2004-05-18 |
| 6737354 | Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates | Donald Miles, Chidi Chidambaram, Amitabh Jain | 2004-05-18 |
| 6709938 | Source/drain extension fabrication process with direct implantation | Donald Miles, P.R. Chidambaram, Amitabh Jain | 2004-03-23 |
| 6699763 | Disposable spacer technology for reduced cost CMOS processing | Terence Breedijk | 2004-03-02 |
| 6645840 | Multi-layered polysilicon process | Che-Jen Hu | 2003-11-11 |
| 6632718 | Disposable spacer technology for reduced cost CMOS processing | Terence Breedijk | 2003-10-14 |
| 6632747 | Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile | Hiroaki Niimi, Rajesh Khamankar, Sunil Hattangady | 2003-10-14 |
| 6548366 | Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile | Hiroaki Niimi, Rajesh Khamankar | 2003-04-15 |
| 6503846 | Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates | Hiroaki Niimi, James Joseph Chambers, Rajesh Khamankar | 2003-01-07 |
| 6326281 | Integrated circuit isolation | Katherine E. Violette, Rick L. Wise, Stanton Petree Ashburn, Mahalingam Nandakumar | 2001-12-04 |
| 6242295 | Method of fabricating a shallow doped region for a shallow junction transistor | Mark S. Rodder, Katherine E. Violette | 2001-06-05 |
| 6136654 | Method of forming thin silicon nitride or silicon oxynitride gate dielectrics | Robert J. Kraft, Sunil Hattangady | 2000-10-24 |
| 6093659 | Selective area halogen doping to achieve dual gate oxide thickness on a wafer | Vincent M. McNeil | 2000-07-25 |
| 6087268 | Method to reduce boron diffusion through gate oxide using sidewall spacers | Thomas C. Holloway | 2000-07-11 |
| 6063670 | Gate fabrication processes for split-gate transistors | Bo-Yang Lin, George R. Misium | 2000-05-16 |
| 6030874 | Doped polysilicon to retard boron diffusion into and through thin gate dielectrics | Stanton Petree Ashburn, Katherine E. Violette, F. Scott Johnson | 2000-02-29 |
| 5818100 | Product resulting from selective deposition of polysilicon over single crystal silicon substrate | Jon S. Owyang | 1998-10-06 |
| 5717238 | Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi R. Padmanabhan, Chi-Yi Kao | 1998-02-10 |
| 5646073 | Process for selective deposition of polysilicon over single crystal silicon substrate and resulting product | Jon S. Owyang | 1997-07-08 |
| 5585286 | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi R. Padmanabhan, Chi-Yi Kao | 1996-12-17 |
| 5336903 | Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures | Mehmet Ozturk, Mahesh K. Sanganeria, Stanton Petree Ashburn, Jimmie J. Wortman | 1994-08-09 |
| 5242847 | Selective deposition of doped silion-germanium alloy on semiconductor substrate | Mehmet Ozturk, Mahesh K. Sanganeria, Stanton Petree Ashburn | 1993-09-07 |
| 5162246 | Selective germanium deposition on silicon and resulting structures | Mehmet Ozturk, Jimmie J. Wortman | 1992-11-10 |