Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8114784 | Laminated stress overlayer using In-situ multiple plasma treatments for transistor improvement | Haowen Bu, Rajesh Khamankar | 2012-02-14 |
| 7514309 | Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process | Seetharaman Sridhar, Craig Hall, Antonio Luis Pacheco Rotondaro | 2009-04-07 |
| 6956267 | Semiconductor with a nitrided silicon gate oxide and method | Sunil Hattangady, Jaideep Mavoori, Rajesh Khamankar | 2005-10-18 |
| 6764909 | Structure and method of MOS transistor having increased substrate resistance | Craig T. Salling, Zhiqiang Wu | 2004-07-20 |
| 6730556 | Complementary transistors with controlled drain extension overlap | Zhiqiang Wu | 2004-05-04 |
| 6716695 | Semiconductor with a nitrided silicon gate oxide and method | Sunil Hattangady, Jaideep Mavoori, Rajesh Khamankar | 2004-04-06 |
| 6645840 | Multi-layered polysilicon process | Douglas T. Grider | 2003-11-11 |
| 6627955 | Structure and method of MOS transistor having increased substrate resistance | Craig T. Salling, Zhiqiang Wu | 2003-09-30 |