Issued Patents All Time
Showing 451–475 of 636 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8436458 | Flip-chip, face-up and face-down wirebond combination package | Richard Dewitt Crisp, Wael Zohni | 2013-05-07 |
| 8436457 | Stub minimization for multi-die wirebond assemblies with parallel windows | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2013-05-07 |
| 8436477 | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2013-05-07 |
| 8432045 | Conductive pads defined by embedded traces | — | 2013-04-30 |
| 8431435 | Edge connect wafer level stacking | Vage Oganesian | 2013-04-30 |
| 8426957 | Edge connect wafer level stacking | Vage Oganesian | 2013-04-23 |
| 8410618 | Microelectronic assembly with joined bond elements having lowered inductance | Philip Damberg, Philip R. Osborn | 2013-04-02 |
| 8405196 | Chips having rear contacts connected by through vias to front contacts | Kenneth Honer, David B. Tuckerman, Vage Oganesian | 2013-03-26 |
| 8405207 | Stub minimization for wirebond assemblies without windows | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2013-03-26 |
| 8378478 | Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts | Kishor Desai, Wael Zohni | 2013-02-19 |
| 8378487 | Wafer level chip package and a method of fabricating thereof | Teck-Gyu Kang, Guilian Gao | 2013-02-19 |
| RE44019 | Stacked semiconductor module | Thomas F. Fox, Sayeh Khalili, David Nguyen, Richard E. Warmke, Xingchao Yuan | 2013-02-19 |
| 8349654 | Method of fabricating stacked packages with bridging traces | — | 2013-01-08 |
| 8345441 | Stub minimization for multi-die wirebond assemblies with parallel windows | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2013-01-01 |
| 8338963 | Multiple die face-down stacking for two or more die | Wael Zohni, Richard Dewitt Crisp, Ilyas Mohammed | 2012-12-25 |
| 8329581 | Microelectronic packages and methods therefor | Masud Beroz, Teck-Gyu Kang, Yoichi Kubota, Sridhar Krishnan, John Riley +1 more | 2012-12-11 |
| 8330272 | Microelectronic packages with dual or multiple-etched flip-chip connectors | — | 2012-12-11 |
| 8310036 | Chips having rear contacts connected by through vias to front contacts | Kenneth Honer, David B. Tuckerman, Vage Oganesian | 2012-11-13 |
| 8304881 | Flip-chip, face-up and face-down wirebond combination package | Richard Dewitt Crisp, Wael Zohni | 2012-11-06 |
| 8299626 | Microelectronic package | Ilyas Mohammed, Sean Moran, Wei-Shun Wang, Ellis Chau, Christopher Wade | 2012-10-30 |
| 8278764 | Stub minimization for multi-die wirebond assemblies with orthogonal windows | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2012-10-02 |
| 8269357 | Microelectronic assembly with impedance controlled wirebond and conductive reference element | Brian Marcucci | 2012-09-18 |
| 8254155 | Stub minimization for multi-die wirebond assemblies with orthogonal windows | Richard Dewitt Crisp, Wael Zohni, Frank Lambrecht | 2012-08-28 |
| 8253259 | Microelectronic assembly with impedance controlled wirebond and reference wirebond | Brian Marcucci | 2012-08-28 |
| 8241959 | Microelectronic packages fabricated at the wafer level and methods therefor | Giles Humpston | 2012-08-14 |