Issued Patents All Time
Showing 126–150 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9613174 | Common template for electronic article | William Wu Shen, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan, Chao-Yang Yeh +2 more | 2017-04-04 |
| 9508844 | Semiconductor arrangement and formation thereof | I-Wen Wu, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Chao-Hsun Wang | 2016-11-29 |
| 9471742 | Method for displaying timing information of an integrated circuit floorplan in real time | Yi-Lin Chuang, Huang-Yu Chen | 2016-10-18 |
| 9431064 | Memory circuit and cache circuit configuration | Hsien-Hsin Sean Lee, William Wu Shen | 2016-08-30 |
| 9406597 | Integrated circuit system with distributed power supply comprising interposer and voltage regulator | Shyh-An Chi, Mark Shane Peng | 2016-08-02 |
| 9391110 | Wafer on wafer stack method of forming and method of using the same | Sandeep Kumar Goel | 2016-07-12 |
| 9222086 | Compositions and methods for silencing genes expressed in cancer | Adam Judge, Ian MacLachlan, Snorri S. Thorgeirsson | 2015-12-29 |
| 9158324 | Substrate bias control circuit | Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee | 2015-10-13 |
| 9064715 | Networking packages based on interposers | Mark Shane Peng, Shyh-An Chi | 2015-06-23 |
| 9003338 | Common template for electronic article | William Wu Shen, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan, Chao-Yang Yeh +2 more | 2015-04-07 |
| 9003347 | System and method for designing cell rows | Wu-An Kuo | 2015-04-07 |
| 8898608 | Method for displaying timing information of an integrated circuit floorplan | Yi-Lin Chuang, Huang-Yu Chen | 2014-11-25 |
| 8860448 | Test schemes and apparatus for passive interposers | Mill-Jer Wang, Tan-Li Chou | 2014-10-14 |
| 8863062 | Methods and apparatus for floorplanning and routing co-design | Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen | 2014-10-14 |
| 8716855 | Integrated circuit system with distributed power supply comprising interposer and voltage regulator module | Shyh-An Chi, Mark Shane Peng | 2014-05-06 |
| 8707238 | Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs | Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel +1 more | 2014-04-22 |
| 8701070 | Group bounding box region-constrained placement for integrated circuit design | Yi-Lin Chuang, Chun-Cheng Ku, Shao-Yu Wang, Wei-Pin Changchien, Chin-Chou Liu | 2014-04-15 |
| 8631377 | System and method for designing cell rows with differing cell heights | Wu-An Kuo | 2014-01-14 |
| 8552795 | Substrate bias control circuit for system on chip | Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee | 2013-10-08 |
| 8434032 | Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design | Lee-Chung Lu, Wei-Li Chen, Tan-Li Chou, Kheng Guan (Nigel) Tan, Shi-Hung Wang | 2013-04-30 |
| 8276110 | Reducing voltage drops in power networks using unused spaces in integrated circuits | Dinesh Baviskar, Wen-Hao Chen, Chung-Sheng Yuan, Mark Shane Peng | 2012-09-25 |
| 8242826 | Retention flip-flop | Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee | 2012-08-14 |
| 8227443 | Silencing of CSN5 gene expression using interfering RNA | Ian MacLachlan, Adam Judge, Snorri S. Thorgeirsson | 2012-07-24 |
| 8113412 | Methods for detecting defect connections between metal bumps | Nan-Hsin Tseng, Chin-Chou Liu, Ji-Jan Chen, Wei-Pin Changchien, Chien-Hui Chen | 2012-02-14 |
| 7297520 | Large circular sense molecule array | Jong-Gu Park | 2007-11-20 |