Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334388 | Isolation structure and a self-aligned capping layer formed thereon | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2025-06-17 |
| 12324202 | Semiconductor device structure and method for forming the same | Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, Chen-Ming Lee +2 more | 2025-06-03 |
| 12283630 | Epitaxial source/drain structures for multigate devices and methods of fabricating thereof | Chen-Ming Lee, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang | 2025-04-22 |
| 12266703 | Dielectric structures for semiconductor device structures | Shih-Che Lin, Po-Yu Huang, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang +2 more | 2025-04-01 |
| 12224324 | Method of forming backside power rails | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2025-02-11 |
| 12125879 | Epitaxial source/drain structure and method | Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu +2 more | 2024-10-22 |
| 12119378 | Methods of forming epitaxial source/drain features in semiconductor devices | Jia-Heng Wang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2024-10-15 |
| 12080769 | Contact structure with silicide and method for forming the same | Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, Shih-Chieh Wu, Chen-Ming Lee +2 more | 2024-09-03 |
| 12068200 | Backside via with a low-k spacer | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2024-08-20 |
| 12068396 | Parasitic capacitance reduction | Jia-Heng Wang, Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2024-08-20 |
| 12068378 | Semiconductor devices with backside via and methods thereof | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2024-08-20 |
| 11968817 | Source/drain contact having a protruding segment | Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang +1 more | 2024-04-23 |
| 11876135 | Epitaxial source/drain structures for multigate devices and methods of fabricating thereof | Chen-Ming Lee, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang | 2024-01-16 |
| 11855161 | Semiconductor device contact structures and methods of fabricating thereof | Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2023-12-26 |
| 11843028 | Isolation features and methods of fabricating the same | Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu | 2023-12-12 |
| 11791387 | Semiconductor devices with backside via and methods thereof | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2023-10-17 |
| 11784222 | Epitaxial source/drain structure and method | Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu +2 more | 2023-10-10 |
| 11777004 | Fin field effect transistor (FinFET) device structure and method for forming the same | Kai-Hsuan Lee, Chen-Ming Lee, Jian-Hao Chen, Fu-Kai Yang, Feng-Cheng Yang +2 more | 2023-10-03 |
| 11757022 | Parasitic capacitance reduction | Jia-Heng Wang, Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2023-09-12 |
| 11728394 | Method of forming backside power rails | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2023-08-15 |
| 11694931 | Metal gate structure cutting process | Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu +1 more | 2023-07-04 |
| 11615987 | Backside via with a low-k spacer | Po-Yu Huang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2023-03-28 |
| 11532507 | Semiconductor device and method | Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko +2 more | 2022-12-20 |
| 11302802 | Parasitic capacitance reduction | Jia-Heng Wang, Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang | 2022-04-12 |
| 11264393 | Source/drain contact having a protruding segment | Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang +1 more | 2022-03-01 |