SW

Shih-Chieh Wu

TSMC: 8 patents #3,198 of 12,232Top 30%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
IT Intai Technology: 1 patents #10 of 21Top 50%
NU National Chiao Tung University: 1 patents #506 of 1,517Top 35%
NU National Tsing Hua University: 1 patents #672 of 2,036Top 35%
Overall (All Time): #397,713 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDate
12419102 Semiconductor devices Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh +1 more 2025-09-16
12363947 Structure and formation method of semiconductor device with contact structures Pang-Chi Wu, Wang-Jung Hsueh, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang +2 more 2025-07-15
12324202 Semiconductor device structure and method for forming the same Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee +2 more 2025-06-03
12080769 Contact structure with silicide and method for forming the same Kai-Hsuan Lee, Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee +2 more 2024-09-03
12068201 Semiconductor devices Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh +1 more 2024-08-20
11721590 Semiconductor device and method Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh +1 more 2023-08-08
11393724 Semiconductor device and method Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh +1 more 2022-07-19
10957604 Semiconductor device and method Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh +1 more 2021-03-23
10260861 Optical measuring system for magnifying displacement, optical measuring apparatus for magnifying displacement and measuring method thereof Dian-Ying LIN, Chen-Tai Lin, Shih-Chang Chuang 2019-04-16
8769454 Register-transfer level (RTL) design checking for exploring simulation and/or synthesis mismatches and ambiguous language semantics using categorization Andy S. Tsay, Kuei Ju Yang 2014-07-01
8687432 Multi-bit resistive-switching memory cell and array Tuo-Hung Hou 2014-04-01
7302655 Method for verifying a circuit design by assigning numerical values to inputs of the circuit design Chun-Yao Wang, Jan-An Hsieh 2007-11-27