AT

Andy S. Tsay

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Fremont, CA: #6,509 of 9,298 inventorsTop 75%
🗺 California: #247,236 of 386,348 inventorsTop 65%
Overall (All Time): #3,113,503 of 4,157,543Top 75%
1
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Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
8769454 Register-transfer level (RTL) design checking for exploring simulation and/or synthesis mismatches and ambiguous language semantics using categorization Kuei Ju Yang, Shih-Chieh Wu 2014-07-01