Issued Patents All Time
Showing 176–200 of 303 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9806171 | Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration | Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Chii-Horng Li | 2017-10-31 |
| 9779980 | Uniform shallow trench isolation regions and the method of forming the same | Yu-Ling Liou, Chih-Tang Peng, Pei-Ren Jeng, Hao-Ming Lien | 2017-10-03 |
| 9768044 | Apparatus and methods for annealing wafers | Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Pei-Ren Jeng | 2017-09-19 |
| 9754818 | Via patterning using multiple photo multiple etch | Jung-Hau Shiu, Chung-Chi Ko, Wen-Kuo Hsieh, Yu-Yun Peng | 2017-09-05 |
| 9755077 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li | 2017-09-05 |
| 9754822 | Interconnect structure and method | Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao +3 more | 2017-09-05 |
| 9728641 | Semiconductor device and fabrication method thereof | Yen-Ru Lee, Ming-Hua Yu, Chii-Horng Li, Pang-Yen Tsai, Lilly Su +2 more | 2017-08-08 |
| 9727049 | Qualitative fault detection and classification system for tool condition monitoring and associated methods | Chia-Tong Ho, Po-Feng Tsai, Jung-Chang Chen, Jo Fei Wang, Jong-I Mou +1 more | 2017-08-08 |
| 9698243 | Transistor strain-inducing scheme | Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Chii-Horng Li | 2017-07-04 |
| 9691898 | Germanium profile for channel strain | Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li | 2017-06-27 |
| 9679804 | Multi-patterning to form vias with straight profiles | Chun-Kai Chen, Jung-Hau Shiu, Chia-Cheng Chou, Chung-Chi Ko, Chih-Hao Chen +1 more | 2017-06-13 |
| 9666686 | MOS devices having epitaxy regions with reduced facets | Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tsz-Mei Kwok | 2017-05-30 |
| 9653574 | Selective etching in the formation of epitaxy regions in MOS devices | Yu-Hung Cheng, Chii-Horng Li | 2017-05-16 |
| 9647066 | Dummy FinFET structure and method of making same | Chang-Shen Lu, Chih-Tang Peng, Tai-Chun Huang, Pei-Ren Jeng, Hao-Ming Lien +2 more | 2017-05-09 |
| 9647111 | Advanced forming method and structure of local mechanical strained transistor | Chien-Hao Chen | 2017-05-09 |
| 9612056 | Wafer holder with varying surface property | Yi-Hung Lin, Li-Ting Wang | 2017-04-04 |
| 9601619 | MOS devices with non-uniform P-type impurity profile | Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li | 2017-03-21 |
| 9583483 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li | 2017-02-28 |
| 9564488 | Strained isolation regions | Mong-Song Liang, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng | 2017-02-07 |
| 9517539 | Wafer susceptor with improved thermal characteristics | Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Chii-Horng Li | 2016-12-13 |
| 9484265 | Structure and method for semiconductor device | Yi-Jing Lee, Chii-Horng Li, Kun-Mu Li | 2016-11-01 |
| 9443961 | Semiconductor strips with undercuts and methods for forming the same | Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien +1 more | 2016-09-13 |
| 9437712 | High performance self aligned contacts and method of forming same | Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee | 2016-09-06 |
| 9425287 | Reducing variation by using combination epitaxy growth | Yu-Hung Cheng, Yi-Hung Lin, Chii-Horng Li | 2016-08-23 |
| 9412648 | Via patterning using multiple photo multiple etch | Jung-Hau Shiu, Chung-Chi Ko, Wen-Kuo Hsieh, Yu-Yun Peng | 2016-08-09 |