Issued Patents All Time
Showing 101–125 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8435802 | Conductor layout technique to reduce stress-induced void formations | Min-hwa Chi, Chih-Hsiang Yao | 2013-05-07 |
| 8253177 | Strained channel transistor | Ming-Hua Yu | 2012-08-28 |
| 7791070 | Semiconductor device fault detection system and method | Chih-Hsiang Yao, Kuan-Shou Chi, Wen-Kai Wan | 2010-09-07 |
| 7777338 | Seal ring structure for integrated circuit chips | Chih-Hsiang Yao, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuoh Liang, Wen-Kai Wan +1 more | 2010-08-17 |
| 7772701 | Integrated circuit having improved interconnect structure | Chih-Hsiang Yao, Mong-Song Liang | 2010-08-10 |
| 7741714 | Bond pad structure with stress-buffering layer capping interconnection metal layer | Chih-Hsiang Yao, Wen-Kai Wan | 2010-06-22 |
| 7700452 | Strained channel transistor | Ming-Hua Yu | 2010-04-20 |
| 7592710 | Bond pad structure for wire bonding | Chin-Chiu Hsia, Chih-Hsiang Yao, Chih-Tang Peng | 2009-09-22 |
| 7470994 | Bonding pad structure and method for making the same | Chih-Hsiang Yao, Chin-Chiu Hsia | 2008-12-30 |
| 7265436 | Non-repeated and non-uniform width seal ring structure | Chih-Hsiang Yao, Kuan-Shou Chi | 2007-09-04 |
| 7253531 | Semiconductor bonding pad structure | Chih-Hsiang Yao, Kuan-Shou Chi, Ming-Ta Lei, Chin-Chiu Hsia | 2007-08-07 |
| 7244673 | Integration film scheme for copper / low-k interconnect | Chih-Hsiang Yao, Yih-Hsiung Lin, Tien-I Bao, Bi-Trong Chen, Yung-Cheng Lu | 2007-07-17 |
| 7151052 | Multiple etch-stop layer deposition scheme and materials | Chih-Hsiang Yao, Kuan-Shou Chi, Chin-Chiu Hsia, Mong-Song Liang | 2006-12-19 |
| 7098077 | Semiconductor chip singulation method | Kuan-Shou Chi, Chih-Hsiang Yao | 2006-08-29 |
| 7081679 | Structure and method for reinforcing a bond pad on a chip | Chih-Hsiang Yao | 2006-07-25 |
| 7074629 | Test patterns for measurement of effective vacancy diffusion area | Chih-Hsiang Yao | 2006-07-11 |
| 7023090 | Bonding pad and via structure design | Tze-Liang Lee | 2006-04-04 |
| 6927498 | Bond pad for flip chip package | Chih-Hsiang Yao, Ching-Hua Hsieh | 2005-08-09 |
| 6864701 | Test patterns for measurement of effective vacancy diffusion area | Chih-Hsiang Yao | 2005-03-08 |
| 6858944 | Bonding pad metal layer geometry design | Tze-Liang Lee | 2005-02-22 |
| 6831365 | Method and pattern for reducing interconnect failures | Chih-Hsiang Yao, Wen-Kai Wan, Chin-Chiu Hsia | 2004-12-14 |
| 6825541 | Bump pad design for flip chip bumping | Tze-Liang Lee | 2004-11-30 |
| 6787803 | Test patterns for measurement of low-k dielectric cracking thresholds | Chih-Hsiang Yao | 2004-09-07 |
| 6369439 | Strip of semiconductor package | Su Tao, Kuo-Pin Yang | 2002-04-09 |
| 6229702 | Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability | Su Tao, Chin-Long Wu, Han-Hsiang Huang, Shih-Kuang Chen, Shin-Hua Chao | 2001-05-08 |