Issued Patents All Time
Showing 101–125 of 168 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773671 | Material composition and process for mitigating assist feature pattern transfer | Meng CHEN, Chen-Hau Wu, Meng-Wei Chen, Kuei-Shun Chen, Yu-Chin Huang +2 more | 2017-09-26 |
| 9761436 | Mechanisms for forming patterns using multiple lithography processes | Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau | 2017-09-12 |
| 9735140 | Systems and methods for a sequential spacer scheme | Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2017-08-15 |
| 9716032 | Via-free interconnect structure with self-aligned metal line interconnections | Yu-Po Tang, Ken-Hsien Hsieh, Ru-Gun Liu | 2017-07-25 |
| 9711369 | Method for forming patterns with sharp jogs | — | 2017-07-18 |
| 9697325 | System and method for optimization of an imaged pattern of a semiconductor device | Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su | 2017-07-04 |
| 9684236 | Method of patterning a film layer | Ken-Hsien Hsieh, Kuan-Hsin Lo, Wei-Liang Lin, Joy Cheng, Chun-Kuang Chen +5 more | 2017-06-20 |
| 9672320 | Method for integrated circuit manufacturing | Chien-Fu Lee, Chin-Yuan Tseng | 2017-06-06 |
| 9627310 | Semiconductor device with self-aligned interconnects | Ken-Hsien Hsieh, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou | 2017-04-18 |
| 9581900 | Self aligned patterning with multiple resist layers | Ming-Feng Shieh, Chih-Ming Lai, Ken-Hsien Hsieh, Ru-Gun Liu | 2017-02-28 |
| 9576099 | Minimizing harmful effects caused by reticle defects by re-arranging IC layout locally | Chia-Hao Yu | 2017-02-21 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Chih-Ming Lai, Ken-Hsien Hsieh +1 more | 2017-02-07 |
| 9541846 | Homogeneous thermal equalization with active device | — | 2017-01-10 |
| 9529268 | Systems and methods for improving pattern transfer | Chien-Fu Lee, Hoi-Tou Ng | 2016-12-27 |
| 9501601 | Layout optimization of a main pattern and a cut pattern | Kuei-Liang Lu | 2016-11-22 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2016-11-22 |
| 9465906 | System and method for integrated circuit manufacturing | — | 2016-10-11 |
| 9361420 | System and method for optimization of an imaged pattern of a semiconductor device | Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su | 2016-06-07 |
| 9362169 | Self-aligned semiconductor fabrication with fosse features | Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2016-06-07 |
| 9362132 | Systems and methods for a sequential spacer scheme | Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2016-06-07 |
| 9362119 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Ken-Hsien Hsieh, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2016-06-07 |
| 9356021 | Self-alignment for two or more layers and methods of forming same | Ru-Gun Liu, Ken-Hsien Hsieh, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau | 2016-05-31 |
| 9293341 | Mechanisms for forming patterns using multiple lithography processes | — | 2016-03-22 |
| 9245763 | Mechanisms for forming patterns using multiple lithography processes | Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau | 2016-01-26 |
| 9214356 | Mechanisms for forming patterns | Ru-Gun Liu, Chung-Te Lin, Ming-Feng Shieh, Tsai-Sheng Gau | 2015-12-15 |