Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529956 | Active region design layout | Chen-Liang Liao, Cheng-Wei Cheng, Yi-Lii Huang | 2016-12-27 |
| 9431531 | Semiconductor device having drain side contact through buried oxide | Tung-Yang Lin, Hsin-Chih Chiang, Ruey-Hsin Liu | 2016-08-30 |
| 9412863 | Enhanced breakdown voltages for high voltage MOSFETS | Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu | 2016-08-09 |
| 9379179 | Ultra high voltage electrostatic discharge protection device with current gain | Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu | 2016-06-28 |
| 9369175 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2016-06-14 |
| 9343465 | Integrated circuit for high-voltage device protection | Chen-Liang Chu, Ruey-Hsin Liu, Chih-Wen Yao | 2016-05-17 |
| 9324864 | Semiconductor device structure and method for forming the same | Chia-Yao Liang, Chen-Liang Liao, Chih-Hsiao Chen, Yi-Lii Huang | 2016-04-26 |
| 9252019 | Semiconductor device and method for forming the same | Wen-Chi Tsai, Chia-Han Lai, Yung-Chung Chen, Mei-Yun Wang, Chii-Ming Wu +2 more | 2016-02-02 |
| 8901733 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Ching-Cheng Huang, Chuen-Jye Lin, Mou-Shiung Lin | 2014-12-02 |
| 8481418 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2013-07-09 |
| RE43674 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang | 2012-09-18 |
| 8178967 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2012-05-15 |
| 8158508 | Structure and manufacturing method of a chip scale package | Mou-Shiung Lin, Chuen-Jye Lin | 2012-04-17 |
| 8053894 | Surface treatment of metal interconnect lines | Wen-Kai Wan, Yih-Hsiung Lin, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin +1 more | 2011-11-08 |
| 7902679 | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump | Mou-Shiung Lin, Chuen-Jye Lin | 2011-03-08 |
| 7465653 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Ching-Cheng Huang, Chuen-Jye Lin, Mou-Shiung Lin | 2008-12-16 |
| 7439084 | Predictions of leakage modes in integrated circuits | Tang Kok Hiang | 2008-10-21 |
| 7355288 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2008-04-08 |
| 7338890 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2008-03-04 |
| 7271103 | Surface treated low-k dielectric as diffusion barrier for copper metallization | Kuei-Wu Huang, Ai-Sen Liu, Baw-Ching Perng, Wen-Kai Wan, Cheng-Chung Lin +2 more | 2007-09-18 |
| 7253531 | Semiconductor bonding pad structure | Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi, Chin-Chiu Hsia | 2007-08-07 |
| 7176137 | Method for multiple spacer width control | Baw-Ching Perng, Yih-Shung Lin, Ai-Sen Liu, Chia-Hui Lin, Cheng-Chung Lin | 2007-02-13 |
| 7011929 | Method for forming multiple spacer widths | Yih-Shung Lin, Ai-Sen Liu, Cheng-Chung Lin, Baw-Ching Perng, Chia-Hui Lin | 2006-03-14 |
| 6943077 | Selective spacer layer deposition method for forming spacers with different widths | Ai-Sen Liu, Baw-Ching Perng, Yih-Shung Lin, Cheng-Chung Lin, Chia-Hui Lin | 2005-09-13 |
| 6917119 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ching-Cheng Huang, Chuen-Jye Lin | 2005-07-12 |